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| advance information powernp tm npe405h embedded processor data sheet 1 features ibm powerpc tm 405 32-bit risc processor core operating up to 266 mhz pc-100 synchronous dram (sdram) interface operating up to 133 mhz - 32-bit interface for non-ecc applications - 40-bit interface serves 32 bits of data plus 8 check bits for ecc applications external peripheral bus - flash rom/boot rom interface - direct support for 8-, or 16-, or 32-bit sram and external peripherals - up to 8 banks - external mastering supported dma support for external peripherals, internal uarts and memory - scatter-gather chaining supported - four channels pci revision 2.2 compliant interface (32-bit, up to 66mhz) - asynchronous pci bus interface - internal pci bus arbiter which can be disabled for use with an external arbiter up to4 ethernet 10/100mbps (full-duplex) units with a choice of mii, rmii, or smii interfaces. hdlc interface with 32 channels through 2 ports hdlc interface with 8 channels through 8 ports programmable interrupt controllers supports interrupts from a variety of sources - seven external and 49 internal - edge triggered or level-sensitive - positive or negative active - non-critical or critical interrupt to processor core - programmable critical interrupt priority ordering - programmable critical interrupt vector for faster vector processing programmable timers two serial ports (16550 compatible uart) one iic (i 2 c) interface general purpose i/o (gpio) available supports jtag for board level testing internal processor local bus (plb) runs at sdram interface frequency supports powerpc processor boot from pci memory user accessible performance counters description designed specifically to address embedded applications, the npe405h provides a high- performance, low-power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and intrinsically lower power dissipation requirements. this chip contains a high-performance risc processor core, sdram controller, pci bus interface, ethernet interfaces, hdlc interfaces, control for external rom and peripherals, dma with scatter-gather support, serial ports, iic interface, and general purpose i/o. technology: ibm cmos 6sf 0.25 m (0.18 m l eff ) package: 580-ball (35mm) enhanced plastic ball grid array (e-pbga) power (estimated): typical 1.4w, maximum 2.3w while the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made.
advance information powernp tm npe405h embedded processor data sheet 2 contents ordering, pvr, and jtag information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 address map support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 plb to pci interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 sdram memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 external peripheral bus controller (ebc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 iic bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 iic eeprom controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 hdlcex interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 hdlcmp interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 general purpose io (gpio) controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 universal interrupt controller (uic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 10/100 mbps ethernet mac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 performance counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 signal list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 spread spectrum clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 advance information powernp tm npe405h embedded processor data sheet 3 tables sysmem memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 dcr address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 signals listed alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 signals listed by ball assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 signal functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 package thermal specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 sysclk and memclk timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 peripheral interface clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 i/o specifications?00mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 i/o specifications?66mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figures npe405h embedded controller functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 35mm, 580-ball e-pbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 input setup and hold waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 output delay and float timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 advance information powernp tm npe405h embedded processor data sheet 4 ordering, pvr, and jtag information this section provides the part numbering nomenclature for the npe405h. for availability, contact your local ibm sales office. the part number contains a part modifier. this modifier provides for identification of future enhancements (for example, higher performance). each part number also contains a revision code. this refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. the pvr (processor version register) is software accessible and contains additional information about the revision level of the part. refer to the npe405h user? manual for details on the register content. ibm part number key product name order part number 1 processor frequency package rev level pvr value jtag id npe405h 200mhz 35mm, 580 e-pbga 0x414100c0 0x???????? npe405h 200mhz 35mm, 580 e-pbga 0x414100c0 0x???????? npe405h 266mhz 35mm, 580 e-pbga 0x414100c0 0x???????? npe405h 266mhz 35mm, 580 e-pbga 0x414100c0 0x???????? note 1: z at the end of the order part number indicates a tape and reel shipping package. otherwise, the chips are shipped in a tray. ibm part number ibm25npe405h-3da200cx package (e-pbga) processor speed grade 3 reliability case temperature range revision level shipping package* * blank = tray z = tape and reel (-40? to +85?) advance information powernp tm npe405h embedded processor data sheet 5 npe405h embedded controller functional block diagram the npe405h is designed using the ibm microelectronics blue logic tm methodology in which major functional blocks are integrated to create an application-speci? asic product. this approach provides a consistent way to generate complex asics using ibm coreconnect tm bus architecture. note: ibm coreconnect busses provide: 64-bit plb interfaces up to 133mhz 32-bit opb interfaces up to 66mhz address map support the npe405h incorporates two simple and separate address maps. the first is a fixed processor address map that serves the powerpc family of processors. this address map defines the possible contents of various address regions which the processor can access. the second address map is for device configuration registers (dcr). this address map is accessed by software running on the npe405h processor through the use of mtdcr and mfdcr commands. ppc405 processor core dcu icu dcr bus 16kb on-chip peripheral bus (opb) gpio iic mal8 dma bridge processor local bus (plb) sdram pci bridge external bus controller controller clock control reset power mgmt jtag trace timers mmu zmii controller opb arb - 28-bit addr - 13-bit addr - 32-bit data i-cache 8kb d-cache (4-channel) 66 mhz max (async) 133 mhz max 66 mhz max dcrs hdlcex see peripheral interface clock timing table hdlcmp 8 ports 8 channels 32 channels 2 ports -32-bit data external bus master controller interrupt controller universal x2 uart x2 ethernet x4 mii, rmii, smii mal64 mal64 x2 iec advance information powernp tm npe405h embedded processor data sheet 6 sysmem memory address map 4gb system memory function sub function start address end address size local memory/peripherals 1 00000000 7fffffff 2gb pci total 80000000 ef5fffff 1.74gb pci memory 80000000 e7ffffff 1.63gb pci i/o e8000000 e800ffff 64kb reserved e8010000 e87fffff pci i/o e8800000 ebffffff 56mb reserved ec000000 eebfffff pci configuration registers eec00000 eec00007 8b reserved eec00008 eecfffff pci interrupt acknowledge eed00000 eedfffff 1mb reserved eee00000 ef3fffff pci local configuration registers ef400000 ef40003f 64b reserved ef400040 ef5fffff internal peripherals total ef600000 efffffff 10mb uart0 ef600300 ef600307 8b reserved ef600308 ef6003ff uart1 ef600400 ef600407 8b reserved ef600408 ef6004ff iic0 ef600500 ef60051f 32b reserved ef600520 ef6005ff opb arbiter ef600600 ef60063f 64b reserved ef600640 ef6006ff sgpio controller registers ef600700 ef60077f 128b cgpio controller registers ef600780 ef6007ff 128b ethernet 0 controller registers ef600800 ef6008ff 256b ethernet 1 controller registers ef600900 ef6009ff 256b ethernet 2 controller registers ef600a00 ef600aff 256b ethernet 3 controller registers ef600b00 ef600bff 256b reserved ef600c00 ef600c0f . zmii ef600c10 ef600c1f 16b reserved ef600c20 ef60ffff hdlcex ef610000 ef61ffff 64kb hdlcmp ef620000 ef62ffff 64kb reserved ef630000 efffffff expansion rom 2 f0000000 ffdfffff 254mb boot rom 2, 3 ffe00000 ffffffff 2mb notes: 1. the local memory/peripheral area of the memory map can be configured for sdram, rom or peripherals. 2. the boot rom and expansion rom area of the memory map are intended for use by rom or flash-type devices. while locating volatile sdram and sram in this region is supported by the controller it is not recommended that these regions be used for this purpose. 3. when the optional boot from pci memory is selected, the pci boot rom address space begins at fffe 0000 (size is 128kb). advance information powernp tm npe405h embedded processor data sheet 7 dcr address map 4kb device configuration register function base address strap/parameter start address(0:9) end address(0:9) size dcr address space 1 000 3ff 1kw (4kb) 1 reserved 000 00f 16w memory controller registers 010 011 2w external bus controller registers 012 013 2w reserved 014 07f 108w plb registers 080 08f 16w performance counters 090 091 2w reserved 092 09f 14w opb bridge out registers 0a0 0a7 8w reserved 0a8 0af 8w clock, control and reset 0b0 0b7 8w power management 0b8 0bf 8w interrupt controller 0 0c0 0cf 16w interrupt controller 1 0d0 0df 16w reserved 0e0 0ef 16w miscellaneous 0f0 0ff 16w dma controller registers 100 13f 64w reserved 140 17f 64w mal8 registers (ethernet) 180 1ff 128w mal64 registers (hdlcex) 200 27f 128w mal64 registers (hdlcmp) 280 2ff 128w reserved 300 3ff 256w notes: 1. dcr address space is addressable with up to 10 bits (1024 or 1k unique addresses). each unique address represents a single 32-bit (word) register, or 1 kiloword (kw) (which equals 4 kb). advance information powernp tm npe405h embedded processor data sheet 8 plb to pci interface the plb to pci interface core provides a mechanism for connecting pci devices to the local powerpc processor and local memory. this interface is compliant with version 2.2 of the pci specification. features include: internal pci bus arbiter for up to six external devices at pci bus speeds up to 66mhz. internal arbiter use is optional and can be disabled for systems which employ an external arbiter. plb 3.0 compliant plb bus frequency up to 133mhz 64-bit plb master 32-bit plb slave pci bus frequency up to 66mhz - asynchronous operation from 1/8 plb frequency to 66mhz maximum 32-bit pci address/data bus power management: - pci bus power management v1.1 compliant supports 1:1, 2:1, 3:1, 4:1 clock ratios from plb to pci buffering between plb and pci: - pci target 64-byte write post buffer - pci target 96-byte read prefetch buffer - plb slave 8-byte write post buffer - plb slave 64-byte read prefetch buffer error tracking/status supports pci target side con?uration supports processor access to all pci address spaces: - single-byte pci i/o reads and writes - pci memory single-beat and prefetch-burst reads and single-beat writes - single-byte pci con?uration reads and writes (type 0 and type 1) - pci interrupt acknowledge - pci special cycle supports pci target access to all plb address spaces supports powerpc processor boot from pci memory advance information powernp tm npe405h embedded processor data sheet 9 sdram memory controller the npe405h memory controller core provides a low latency access path to sdram memory. a variety of system memory configurations are supported. the memory controller supports up to four logical banks. up to 256mb per bank are supported, up to a maximum of 1gb. memory timings, address and bank sizes, and memory addressing modes are programmable. features include: 11x8 to 13x11 addressing for sdram (2- and 4-bank) memory bus operates at same frequency as plb 32-bit memory interface support programmable address compare for each bank of memory - 4gb of address space industry standard 168-pin dimms are supported (some con?urations) up to 133mhz memory, includes pc133 support 4mb to 256mb per bank programmable address mapping and timing auto refresh page mode accesses with up to 4 open pages sync dram con?uration via mode set command power management (self-refresh) error checking and correction (ecc) support - standard sec/ded coverage - aligned nibble error detect - address error logging - mixed ecc/non-ecc banks - bypass mode external peripheral bus controller (ebc) up to eight rom, eprom, sram, flash, and slave peripheral i/o banks supported up to 66mhz operation burst and non-burst devices 8-, 16-, 32-bit byte-addressable data bus width support latch data on ready, synchronous or asynchronous advance information powernp tm npe405h embedded processor data sheet 10 programmable 2k clock time-out counter with disable for ready programmable access timing per device - 256 wait states for non-burst - 32 burst wait states for ?st access and up to 8 wait states for subsequent accesses - programmable cson, csoff relative to address - programmable oeon, weon, weoff (1 to 4 clock cycles) relative to cs programmable address mapping peripheral device pacing with external ?eady external master interface - write posting from external master - read prefetching on plb for external master reads - bursting capable from external master - allows external master access to all non-ebc plb slaves - external master can control ebc slaves for own access and control dma controller supports the following transfers: - memory-to-memory transfers - buffered peripheral to memory transfers - buffered memory to peripheral transfers four channels scatter/gather capability for programming multiple dma operations 8-, 16-, 32-bit peripheral support (opb and external) 32-bit addressing address increment or decrement internal 32-byte data buffering capability supports internal and external peripherals support for memory mapped peripherals support for peripherals running on slower frequency buses advance information powernp tm npe405h embedded processor data sheet 11 uart two 8-pin uart interfaces provided selectable internal or external serial clock to allow wide range of baud rates register compatibility with ns16550 register set complete status reporting capability transmitter and receiver are each buffered with 16-byte fifos when in fifo mode fully programmable serial-interface characteristics supports dma using internal dma engine iic bus interface compliant with phillips?semiconductors i 2 c speci?ation, dated 1995 operation at 100khz or 400khz 8-bit data 10- or 7-bit address slave transmitter and receiver master transmitter and receiver multiple bus masters supports ?ed v dd iic interface two independent 4 x 1 byte data buffers twelve memory-mapped, fully programmable con?uration registers one programmable interrupt request signal provides full management of all iic bus protocol programmable error recovery iic eeprom controller supports setting of default initial conditions from serial eeprom during system reset. hdlcex interface multichannel hdlc controller core two full-duplex pulse code modulation (pcm) highway ports at speeds up to 8 mbps 32 transmit and 32 receive channels advance information powernp tm npe405h embedded processor data sheet 12 supports hdlc protocol as well as a transparent mode one channel per port, autonomous management of the i-frame and s-frame of the normal response mode (nrm) protocol software emulation of nrm mode hdlcmp interface hdlc controller core providing eight full-duplex serial ports up to 2mbps data rate supports hdlc protocol as well as a transparent mode software emulation of nrm mode general purpose io (gpio) controller two gpio functions - system gpio (sgpio) - communications gpio (cgpio) controller functions and gpio registers are programmed and accessed via memory-mapped opb bus master accesses most gpios are pin-shared with other functions. dcrs control whether a particular pin that has gpio capabilities acts as a gpio or is used for another purpose. both gpio functions have 32 i/os. each gpio output is separately programmable to emulate an open-drain driver (drives to zero, three- stated if output bit is 1) universal interrupt controller (uic) two cascaded universal interrupt controllers (uics) provides the control, status, and communications necessary between the various sources of interrupts and the local powerpc processor. features include: supports 7 external and 49 internal interrupts edge triggered or level-sensitive positive or negative active non-critical or critical interrupt to ppc405 processor core programmable critical interrupt priority ordering programmable critical interrupt vector for faster vector processing advance information powernp tm npe405h embedded processor data sheet 13 10/100 mbps ethernet mac four units capable of full- or half-duplex operation at up to 100mbps zmii bridge to external ethernet phys that support - reduced media independent interface (rmii) or serial media independent interface (smii) for multiple phy applications - media independent interface (mii) for single phy applications dedicated dma channel jtag ieee 1149.1 test access port ibm riscwatch debugger support jtag boundary scan description language (bsdl) performance counters a series of software accessible plb transaction event counters that can be used to analyze plb performance. advance information powernp tm npe405h embedded processor data sheet 14 35mm, 580-ball e-pbga package top view bottom view 135 7 911131517 19 2 4 6 810 12 14 16 18 21 20 22 23 25 24 26 27 29 28 30 31 33 32 34 a b c d e f g h j k l m aa n p r t u v w y ab ac ae ag aj al an ad af ah ak am ap note: all dimensions are in mm. 35.0 35.0 1.0 1.0 0.60 nom 0.60 solder ball 2.65 max a1 corner advance information powernp tm npe405h embedded processor data sheet 15 pin lists the following table lists all the external signals in alphabetical order and shows the ball number on which the signal appears. multiplexed signals are shown with the default signal (following reset) not in brackets and the alternate signal in brackets. the page number listed gives the page in ?ignal functional description?on page 37 where the signals in the indicated interface group begin. signals listed alphabetically (part 1 of 12) signal name ball interface group page av dd power 45 ba0 ba1 sdram 40 banksel0 banksel1 banksel2 banksel3 sdram 40 [be0 ]pcic0 [be1 ]pcic1 [be2 ]pcic2 [be3 ]pcic3 pci 37 busreq external master peripheral 43 cas sdram 40 advance information powernp tm npe405h embedded processor data sheet 16 cgpio0[hdlcmptxclk4][phy1rxd0][phy1rx2d0] cgpio1[hdlcmptxdata4][phy1rxd1][phy1rx2d1] cgpio2[hdlcmptxen4][phy1rxd2][phy1rx3d0] cgpio3[hdlcmprxclk4][phy1rxd3][phy1rx3d1] cgpio4[hdlcmprxdata4][emc1txd0][emc1tx2d0] cgpio5[hdlcmptxclk5][emc1txd1][emc1tx2d1] cgpio6[hdlcmptxdata5][emc1txd2][emc1tx3d0] cgpio7[hdlcmptxen5][emc1txd3][emc1tx3d1] cgpio8[hdlcmprxclk5][phy1rxerr][phy1rx2er] cgpio9[hdlcmprxdata5][phy1crs3dv][phy1rxdv] cgpio10[hdlcmptxclk6][phy1crs][phy1crs2dv] cgpio11[hdlcmptxdata6][emc1txerr][emc1tx3en] cgpio12[hdlcmptxen6][emc1txen][emc1tx2en] cgpio13[hdlcmprxclk6][phy1rxclk] cgpio14[hdlcmprxdata6][phy1col][phy1rx3er] cgpio15[hdlcmptxclk7] cgpio16[hdlcmptxdata7] cgpio17[hdlcmptxen7][phy1txclk] cgpio18[hdlcmprxclk7] cgpio19[hdlcmprxdata7] cgpio20[hdlcmptxen0][uart1_cts ] cgpio21[hdlcmptxen1][uart1_dsr ] cgpio22[hdlcmptxen2][uart1_dcd ] cgpio23[hdlcmptxen3][uart1_ri ] cgpio24[hdlcextxena][uart1_rts ] cgpio25[hdlcextxenb][uart1_dtr ] cgpio26[uart0_cts ] cgpio27[uart0_dsr ] cgpio28[uart0_dcd ] cgpio29[uart0_ri ] cgpio30[uart0_rts ] cgpio31[uart0_dtr ] system 45 clken0 clken1 sdram 40 [dmaack0 ]sgpio13 [dmaack1 ]sgpio14 [dmaack2 ]sgpio15 [dmaack3 ]sgpio16 external slave peripheral 41 [dmareq0 ]sgpio9 [dmareq1 ]sgpio10 [dmareq2 ]sgpio11 [dmareq3 ]sgpio12 external slave peripheral 41 dqm0 dqm1 dqm2 dqm3 sdram 40 dqmcb sdram 40 signals listed alphabetically (part 2 of 12) signal name ball interface group page advance information powernp tm npe405h embedded processor data sheet 17 ecc0 ecc1 ecc2 ecc3 ecc4 ecc5 ecc6 ecc7 sdram 40 emc0mdclk emc0mdio ethernet 38 [emc0sync]emc0txen[emc0tx0en] ethernet 38 emc0txd0[emc0tx0d0][emc0tx0d] emc0txd1[emc0tx0d1][emc0tx1d] emc0txd2[emc0tx1d0][emc0tx2d] emc0txd3[emc0tx1d1][emc0tx3d] ethernet 38 emc0txen[emc0tx0en][emc0sync] ethernet 38 emc0txerr[emc0tx1en] ethernet 38 [emc0tx0en]emc0txen[emc0sync] [emc0tx1en]emc0txerr ethernet 38 emc1txen][emc1tx2en]cgpio12[hdlcmptxen6] [emc1txerr][emc1tx3en]cgpio11[hdlcmptxdata6] [emc1tx2en][emc1txen]cgpio12[hdlcmptxen6] [emc1tx3en][emc1txerr]cgpio11[hdlcmptxdata6] ethernet 38 [emc1txd0][emc1tx2d0]cgpio4[hdlcmprxdata4] [emc1txd1][emc1tx2d1]cgpio5[hdlcmptxclk5] [emc1txd2][emc1tx3d0]cgpio6[hdlcmptxdata5] [emc1txd3][emc1tx3d1]cgpio7[hdlcmptxen5] ethernet 38 [eot0 ][tc0 ]sgpio24 [eot1 ][tc1 ]sgpio25 [eot2 ][tc2 ]sgpio26 [eot3 ][tc3 ]sgpio27 external slave peripheral 41 extack extreq extreset external master peripheral 43 gnd xxx n13-n22 p13-p22 r13-r22 t13-t22 u13-u22 v13-v22 w13-w22 y13-y22 aa13- aa22 ab13- ab22 xxx power note: balls n13-n22, p13-p22, r13-r22, t13- t22, u13-u22, v13-v22, w13-w22, y13- y22, aa13-aa22, and ab13-ab22 are also thermal balls. 45 [gnt ]pcireq0 pci 37 halt system 45 signals listed alphabetically (part 3 of 12) signal name ball interface group page advance information powernp tm npe405h embedded processor data sheet 18 hdlcexrxdataa hdlcexrxdatab hdlc 32-channel 38 hdlcexrxclk hdlc 32-channel 38 hdlcexrxfs hdlc 32-channel 38 hdlcextxdataa hdlcextxdatab hdlc 32-channel 38 hdlcextxclk hdlc 32-channel 38 [hdlcextxena]cgpio24[uart1_rts ] [hdlcextxenb]cgpio25[uart1_dtr ] hdlc 32-channel 38 hdlcmprxclk0 hdlcmprxclk1 hdlcmprxclk2 hdlcmprxclk3 [hdlcmprxclk4]cgpio3[phy1rxd3][phy1rx3d1] [hdlcmprxclk5]cgpio8[phy1rxerr][phy1rx2er] [hdlcmprxclk6]cgpio13[phy1rxclk] [hdlcmprxclk7]cgpio18] hdlc 8-port 38 hdlcmprxdata0 hdlcmprxdata1 hdlcmprxdata2 hdlcmprxdata3 [hdlcmprxdata4]cgpio4[emc1txd0][emc1tx2d0] [hdlcmprxdata5]cgpio9[phy1crs3dv][phy1rxdv] [hdlcmprxdata6]cgpio14[phy1col][phy1rx3er] [hdlcmprxdata7]cgpio19 hdlc 8-port 38 hdlcmptxclk0 hdlcmptxclk1 hdlcmptxclk2 hdlcmptxclk3 [hdlcmptxclk4]cgpio0[phy1rxd0][phy1rx2d0] [hdlcmptxclk5]cgpio5[emc1txd1][emc1tx2d1] [hdlcmptxclk6]cgpio10[phy1crs][phy1crs2dv] [hdlcmptxclk7]cgpio15 hdlc 8-port 38 hdlcmptxdata0 hdlcmptxdata1 hdlcmptxdata2 hdlcmptxdata3 [hdlcmptxdata4]cgpio1[phy1rxd1][phy1rx2d1] [hdlcmptxdata5]cgpio6[emc1txd2][emc1tx3d0] [hdlcmptxdata6]cgpio11[emc1txerr][emc1tx3en] [hdlcmptxdata7]cgpio16 hdlc 8-port 38 [hdlcmptxen0]cgpio20[uart1_cts ] [hdlcmptxen1[cgpio21[uart1_dsr ] [hdlcmptxen2]cgpio22[uart1_dcd ] [hdlcmptxen3]cgpio23[uart1_ri ] [hdlcmptxen4]cgpio2[phyrx3d0] [hdlcmptxen5]cgpio7[emc0tx3d1] [hdlcmptxen6]cgpio12[emc0tx2en] [hdlcmptxen7]cgpio17 hdlc 8-port 38 signals listed alphabetically (part 4 of 12) signal name ball interface group page advance information powernp tm npe405h embedded processor data sheet 19 holdack holdpri holdreq external master peripheral 43 iicscl[iecscl] iicsda[iecsda] internal peripheral 43 [irq0]sgpio17 [irq1]sgpio18 [irq2]sgpio19 [irq3]sgpio20 [irq4]sgpio21 [irq5]sgpio22 [irq6]sgpio23 interrupts 44 memaddr0 memaddr1 memaddr2 memaddr3 memaddr4 memaddr5 memaddr6 memaddr7 memaddr8 memaddr9 memaddr10 memaddr11 memaddr12 sdram 40 memclkout0 memclkout1 sdram 40 signals listed alphabetically (part 5 of 12) signal name ball interface group page advance information powernp tm npe405h embedded processor data sheet 20 memdata0 memdata1 memdata2 memdata3 memdata4 memdata5 memdata6 memdata7 memdata8 memdata9 memdata10 memdata11 memdata12 memdata13 memdata14 memdata15 memdata16 memdata17 memdata18 memdata19 memdata20 memdata21 memdata22 memdata23 memdata24 memdata25 memdata26 memdata27 memdata28 memdata29 memdata30 memdata31 sdram notes: 1. memdata00 is the most significant bit (msb). 2. memdata31 is the least significant bit (lsb) 40 ov dd power 45 signals listed alphabetically (part 6 of 12) signal name ball interface group page advance information powernp tm npe405h embedded processor data sheet 21 pciad0 pciad1 pciad2 pciad3 pciad4 pciad6 pciad7 pciad8 pciad9 pciad10 pciad11 pciad12 pciad13 pciad14 pciad15 pciad16 pciad17 pciad18 pciad19 pciad20 pciad21 pciad22 pciad23 pciad24 pciad25 pciad26 pciad27 pciad28 pciad29 pciad30 pciad31 pci 37 pcic0[be0 ] pcic1[be1 ] pcic2[be2 ] pcic3[be3 ] pci 37 pciclk pci 37 pcidevsel pci 37 pciframe pci 37 pcignt0 [req ] pcignt1 pcignt2 pcignt3 pcignt4 pcignt5 pci 37 pciidsel pci 37 pciint [perwe ] pci 37 pciirdy pci 37 pciparity pci 37 pciperr pci 37 signals listed alphabetically (part 7 of 12) signal name ball interface group page advance information powernp tm npe405h embedded processor data sheet 22 pcireq0 [gnt ] pcireq1 pcireq2 pcireq3 pcireq4 pcireq5 pci 37 pcireset pci 37 pciserr pci 37 pcistop pci 37 pcitrdy pci 37 peraddr4 peraddr5 peraddr6 peraddr7 peraddr8 peraddr9 peraddr10 peraddr11 peraddr12 peraddr13 peraddr14 peraddr15 peraddr16 peraddr17 peraddr18 peraddr19 peraddr20 peraddr21 peraddr22 peraddr23 peraddr24 peraddr25 peraddr26 peraddr27 peraddr28 peraddr29 peraddr30 peraddr31 external slave peripheral 41 perblast external slave peripheral 41 perclk external slave peripheral 41 percs0 [percs1 ]sgpio28 [percs2 ]sgpio29 [percs3 ]sgpio30 [percs4 ]sgpio12[dmareq3 ] [percs5 ]sgpio16[dmaack3 ] [percs6 ]sgpio23[irq6] [percs7 ]sgpio27[eot3 ][tc3 ] external slave peripheral 41 signals listed alphabetically (part 8 of 12) signal name ball interface group page advance information powernp tm npe405h embedded processor data sheet 23 perdata0 perdata1 perdata2 perdata3 perdata4 perdata5 perdata6 perdata7 perdata8 perdata9 perdata10 perdata11 perdata12 perdata13 perdata14 perdata15 perdata16 perdata17 perdata18 perdata19 perdata20 perdata21 perdata22 perdata23 perdata24 perdata25 perdata26 perdata27 perdata28 perdata29 perdata30 perdata31 external slave peripheral note: perdata00 is the most significant bit (msb) on this bus. 41 pererr external slave peripheral 43 peroe external slave peripheral 41 perpar0 perpar1 perpar2 perpar3 external slave peripheral 41 perr/w external slave peripheral 41 perready external slave peripheral 41 perwbe0 perwbe1 perwbe2 perwbe3 external slave peripheral 41 [perwe ]pciint external slave peripheral 37 phy0col[phy0rx1er] ethernet 38 phy0crs[phy0crs0dv] ethernet 38 [phy0crs0dv]phy0crs [phy0crs1dv]phy0rxdv ethernet 38 [phy0refclk]phy0txclk ethernet 38 phy0rxclk ethernet 38 signals listed alphabetically (part 9 of 12) signal name ball interface group page advance information powernp tm npe405h embedded processor data sheet 24 phy0rxdv[phy0crs1dv] ethernet 38 phy0rxd0[phy0rx0d0][phy0rx0d] phy0rxd1[phy0rx0d1][phy0rx1d] phy0rxd2[phy0rx1d0][phy0rx2d] phy0rxd3[phy0rx1d1][phy0rx3d] ethernet 38 phy0rxerr[phy0rx0er] ethernet 38 [phy0rx0er]phy0rxerr [phy0rx1er]phy0col ethernet 38 phy0txclk[phy0refclk] ethernet 38 [phy1col][phy1rx3er]cgpio14[hdlcmprxdata6] ethernet 38 [phy1crs][phy1crs2dv]cgpio10[hdlcmptxclk6] ethernet 38 [phy1crs2dv][phy1crs]cgpio10[hdlcmptxclk6] [phy1crs3dv][phy1rxdv]cgpio9[hdlcmprxdata5] ethernet 38 [phy1rxclk]cgpio13[hdlcmprxclk6] ethernet 38 [phy1rxdv][phy1crs3dv]cgpio9[hdlcmprxdata5] ethernet 38 [phy1rxd0][phy1rx2d0]cgpio0[hdlcmptxclk4] [phy1rxd1][phy1rx2d1]cgpio1[hdlcmptxdata4] [phy1rxd2][phy1rx3d0]cgpio2[hdlcmptxen4] [phy1rxd3][phy1rx3d1]cgpio3[hdlcmprxclk4] ethernet 38 [phy1rxerr][phy1rx2er]cgpio8[hdlcmprxclk5] ethernet 38 [phy1rx2er][phy1rxerr]cgpio8[hdlcmprxclk5] [phy1rx3er][phy1col]cgpio14[hdlcmprxdata6] ethernet 38 [phy1txclk]cgpio17[hdlcmptxen7] ethernet 38 ras sdram 40 [req ]pcignt0 pci 37 reserved other 45 sgpio0 sgpio1[ts1e] sgpio2[ts2e] sgpio3[ts1o] sgpio4[ts2o] sgpio5[ts3] sgpio6[ts4] sgpio7[ts5] sgpio8[ts6] system 45 sgpio9[dmareq0 ] sgpio10[dmareq1 ] sgpio11[dmareq2 ] sgpio12[dmareq3 ][percs4 ] system 45 sgpio13[dmaack0 ] sgpio14[dmaack1 ] sgpio15[dmaack2 ] sgpio16[dmaack3 ][percs5 ] system 45 signals listed alphabetically (part 10 of 12) signal name ball interface group page advance information powernp tm npe405h embedded processor data sheet 25 sgpio17[irq0 sgpio18[irq1] sgpio19[irq2] sgpio20[irq3] sgpio21[irq4] sgpio22[irq5] sgpio23[irq6][percs6 ] system 45 sgpio24[eot0 ][tc0 ] sgpio25[eot1 ][tc1 ] sgpio26[eot2 ][tc2 ] sgpio27[eot3 ][tc3 ][percs7 ] system 45 sgpio28[percs1 ] sgpio29[percs2 ] sgpio30[percs3 ] system 45 sgpio31[trcclk] system 45 sysclk system 45 syserr system 45 sysreset system 45 tck jtag 44 [tc0 ][eot0 ]sgpio24 [tc1 ][eot1 ]sgpio25 [tc2 ][eot2 ]sgpio26 [tc3 ][eot3 ]sgpio27 external slave peripheral 41 tdi jtag 44 tdo jtag 44 testen system 45 tmrclk system 45 tms jtag 44 trcclk trace 45 trst jtag 44 [ts1e]sgpio1 [ts2e]sgpio2 [ts1o]sgpio3 [ts2o]sgpio4 [ts3]sgpio5 [ts4]sgpio6 [ts5]sgpio7 [ts6]sgpio8 trace 45 [uart0_cts ]cgpio26 [uart0_dcd ]cgpio28 [uart0_dsr ]cgpio27 [uart0_dtr ]cgpio31 [uart0_ri ]cgpio29 [uart0_rts ]cgpio30 uart0_rx uart0_tx internal peripheral 43 signals listed alphabetically (part 11 of 12) signal name ball interface group page advance information powernp tm npe405h embedded processor data sheet 26 [uart1_cts ]cgpio20[hdlcmptxen0] [uart1_dcd ]cgpio22[hdlcmptxen2] [uart1_dsr ]cgpio21[hdlcmptxen1] [uart1_dtr ]cgpio25[hdlcmptxenb] [uart1_ri ]cgpio23[hdlcmptxen3] [uart1_rts ]cgpio24[hdlcmptxena] uart1_rx uart1_tx internal peripheral 43 uartserclk internal peripheral 43 v dd power 45 we sdram 40 signals listed alphabetically (part 12 of 12) signal name ball interface group page advance information powernp tm npe405h embedded processor data sheet 27 signals listed by ball assignment (part 1 of 9) ball signal name ball signal name ball signal name ball signal name a01 b01 c01 d01 a02 b02 c02 d02 a03 b03 c03 d03 a04 b04 c04 d04 a05 b05 c05 d05 a06 b06 c06 d06 a07 b07 c07 d07 a08 b08 c08 d08 a09 b09 c09 d09 a10 b10 c10 d10 a11 a11 c11 d11 a12 b12 c12 d12 a13 b13 c13 d13 a14 b14 c14 d14 a15 b15 c15 d15 a16 b16 c16 d16 a17 b17 c17 d17 a18 b18 c18 d18 a19 b19 c19 d19 a20 b20 c20 d20 a21 b21 c21 d21 a22 b22 c22 d22 a23 b23 c23 d23 a24 b24 c24 d24 a25 b25 c25 d25 a26 b26 c26 d26 a27 b27 c27 d27 a28 b28 c28 d28 a29 b29 c29 d29 a30 b30 c30 d30 a31 b31 c31 d31 a32 b32 c32 d32 a33 b33 c33 d33 a34 b34 c34 d34 advance information powernp tm npe405h embedded processor data sheet 28 e01 f01 g01 h01 e02 f02 g02 h02 e03 f03 g03 h03 e04 f04 g04 h04 e05 no ball f05 no ball g05 no ball h05 no ball e06 no ball f06 no ball g06 no ball h06 no ball e07 no ball f07 no ball g07 no ball h07 no ball e08 no ball f08 no ball g08 no ball h08 no ball e09 no ball f09 no ball g09 no ball h09 no ball e10 no ball f10 no ball g10 no ball h10 no ball e11 no ball a11 no ball g11 no ball h11 no ball e12 no ball f12 no ball g12 no ball h12 no ball e13 no ball f13 no ball g13 no ball h13 no ball e14 no ball f14 no ball g14 no ball h14 no ball e15 no ball f15 no ball g15 no ball h15 no ball e16 no ball f16 no ball g16 no ball h16 no ball e17 no ball f17 no ball g17 no ball h17 no ball e18 no ball f18 no ball g18 no ball h18 no ball e19 no ball f19 no ball g19 no ball h19 no ball e20 no ball f20 no ball g20 no ball h20 no ball e21 no ball f21 no ball g21 no ball h21 no ball e22 no ball f22 no ball g22 no ball h22 no ball e23 no ball f23 no ball g23 no ball h23 no ball e24 no ball f24 no ball g24 no ball h24 no ball e25 no ball f25 no ball g25 no ball h25 no ball e26 no ball f26 no ball g26 no ball h26 no ball e27 no ball f27 no ball g27 no ball h27 no ball e28 no ball f28 no ball g28 no ball h28 no ball e29 no ball f29 no ball g29 no ball h29 no ball e30 no ball f30 no ball g30 no ball h30 no ball e31 f31 g31 h31 e32 f32 g32 h32 e33 f33 g33 h33 e34 f34 g34 h34 signals listed by ball assignment (part 2 of 9) ball signal name ball signal name ball signal name ball signal name advance information powernp tm npe405h embedded processor data sheet 29 j01 k01 l01 m01 j02 k02 l02 m02 j03 k03 l03 m03 j04 k04 l04 m04 j05 no ball k05 no ball l05 no ball m05 no ball j06 no ball k06 no ball l06 no ball m06 no ball j07 no ball k07 no ball l07 no ball m07 no ball j08 no ball k08 no ball l08 no ball m08 no ball j09 no ball k09 no ball l09 no ball m09 no ball j10 no ball k10 no ball l10 no ball m10 no ball j11 no ball k11 no ball l11 no ball m11 no ball j12 no ball k12 no ball l12 no ball m12 no ball j13 no ball k13 no ball l13 no ball m13 no ball j14 no ball k14 no ball l14 no ball m14 no ball j15 no ball k15 no ball l15 no ball m15 no ball j16 no ball k16 no ball l16 no ball m16 no ball j17 no ball k17 no ball l17 no ball m17 no ball j18 no ball k18 no ball l18 no ball m18 no ball j19 no ball k19 no ball l19 no ball m19 no ball j20 no ball k20 no ball l20 no ball m20 no ball j21 no ball k21 no ball l21 no ball m21 no ball j22 no ball k22 no ball l22 no ball m22 no ball j23 no ball k23 no ball l23 no ball m23 no ball j24 no ball k24 no ball l24 no ball m24 no ball j25 no ball k25 no ball l25 no ball m25 no ball j26 no ball k26 no ball l26 no ball m26 no ball j27 no ball k27 no ball l27 no ball m27 no ball j28 no ball k28 no ball l28 no ball m28 no ball j29 no ball k29 no ball l29 no ball m29 no ball j30 no ball k30 no ball l30 no ball m30 no ball j31 k31 l31 m31 j32 k32 l32 m32 j33 k33 l33 m33 j34 k34 l34 m34 signals listed by ball assignment (part 3 of 9) ball signal name ball signal name ball signal name ball signal name advance information powernp tm npe405h embedded processor data sheet 30 n01 p01 r01 t01 n02 p02 r02 t02 n03 p03 r03 t03 n04 p04 r04 t04 n05 no ball p05 no ball r05 no ball t05 no ball n06 no ball p06 no ball r06 no ball t06 no ball n07 no ball p07 no ball r07 no ball t07 no ball n08 no ball p08 no ball r08 no ball t08 no ball n09 no ball p09 no ball r09 no ball t09 no ball n10 no ball p10 no ball r10 no ball t10 no ball n11 no ball p11 no ball r11 no ball t11 no ball n12 no ball p12 no ball r12 no ball t12 no ball n13 gnd p13 gnd r13 gnd t13 gnd n14 gnd p14 gnd r14 gnd t14 gnd n15 gnd p15 gnd r15 gnd t15 gnd n16 gnd p16 gnd r16 gnd t16 gnd n17 gnd p17 gnd r17 gnd t17 gnd n18 gnd p18 gnd r18 gnd t18 gnd n19 gnd p19 gnd r19 gnd t19 gnd n20 gnd p20 gnd r20 gnd t20 gnd n21 gnd p21 gnd r21 gnd t21 gnd n22 gnd p22 gnd r22 gnd t22 gnd n23 no ball p23 no ball r23 no ball t23 no ball n24 no ball p24 no ball r24 no ball t24 no ball n25 no ball p25 no ball r25 no ball t25 no ball n26 no ball p26 no ball r26 no ball t26 no ball n27 no ball p27 no ball r27 no ball t27 no ball n28 no ball p28 no ball r28 no ball t28 no ball n29 no ball p29 no ball r29 no ball t29 no ball n30 no ball p30 no ball r30 no ball t30 no ball n31 p31 r31 t31 n32 p32 r32 t32 n33 p33 r33 t33 n34 p34 r34 t34 signals listed by ball assignment (part 4 of 9) ball signal name ball signal name ball signal name ball signal name advance information powernp tm npe405h embedded processor data sheet 31 u01 v01 w01 y01 u02 v02 w02 y02 u03 v03 w03 y03 u04 v04 w04 y04 u05 no ball v05 no ball w05 no ball y05 no ball u06 no ball v06 no ball w06 no ball y06 no ball u07 no ball v07 no ball w07 no ball y07 no ball u08 no ball v08 no ball w08 no ball y08 no ball u09 no ball v09 no ball w09 no ball y09 no ball u10 no ball v10 no ball w10 no ball y10 no ball u11 no ball v11 no ball w11 no ball y11 no ball u12 no ball v12 no ball w12 no ball y12 no ball u13 gnd v13 gnd w13 gnd y13 gnd u14 gnd v14 gnd w14 gnd y14 gnd u15 gnd v15 gnd w15 gnd y15 gnd u16 gnd v16 gnd w16 gnd y16 gnd u17 gnd v17 gnd w17 gnd y17 gnd u18 gnd v18 gnd w18 gnd y18 gnd u19 gnd v19 gnd w19 gnd y19 gnd u20 gnd v20 gnd w20 gnd y20 gnd u21 gnd v21 gnd w21 gnd y21 gnd u22 gnd v22 gnd w22 gnd y22 gnd u23 no ball v23 no ball w23 no ball y23 no ball u24 no ball v24 no ball w24 no ball y24 no ball u25 no ball v25 no ball w25 no ball y25 no ball u26 no ball v26 no ball w26 no ball y26 no ball u27 no ball v27 no ball w27 no ball y27 no ball u28 no ball v28 no ball w28 no ball y28 no ball u29 no ball v29 no ball w29 no ball y29 no ball u30 no ball v30 no ball w30 no ball y30 no ball u31 v31 w31 y31 u32 v32 w32 y32 u33 v33 w33 y33 u34 v34 w34 y34 signals listed by ball assignment (part 5 of 9) ball signal name ball signal name ball signal name ball signal name advance information powernp tm npe405h embedded processor data sheet 32 aa01 ab01 ac01 ad01 aa02 ab02 ac02 ad02 aa03 ab03 ac03 ad03 aa04 ab04 ac04 ad04 aa05 no ball ab05 no ball ac05 no ball ad05 no ball aa06 no ball ab06 no ball ac06 no ball ad06 no ball aa07 no ball ab07 no ball ac07 no ball ad07 no ball aa08 no ball ab08 no ball ac08 no ball ad08 no ball aa09 no ball ab09 no ball ac09 no ball ad09 no ball aa10 no ball ab10 no ball ac10 no ball ad10 no ball aa11 no ball ab11 no ball ac11 no ball ad11 no ball aa12 no ball ab12 no ball ac12 no ball ad12 no ball aa13 gnd ab13 gnd ac13 no ball ad13 no ball aa14 gnd ab14 gnd ac14 no ball ad14 no ball aa15 gnd ab15 gnd ac15 no ball ad15 no ball aa16 gnd ab16 gnd ac16 no ball ad16 no ball aa17 gnd ab17 gnd ac17 no ball ad17 no ball aa18 gnd ab18 gnd ac18 no ball ad18 no ball aa19 gnd ab19 gnd ac19 no ball ad19 no ball aa20 gnd ab20 gnd ac20 no ball ad20 no ball aa21 gnd ab21 gnd ac21 no ball ad21 no ball aa22 gnd ab22 gnd ac22 no ball ad22 no ball aa23 no ball ab23 no ball ac23 no ball ad23 no ball aa24 no ball ab24 no ball ac24 no ball ad24 no ball aa25 no ball ab25 no ball ac25 no ball ad25 no ball aa26 no ball ab26 no ball ac26 no ball ad26 no ball aa27 no ball ab27 no ball ac27 no ball ad27 no ball aa28 no ball ab28 no ball ac28 no ball ad28 no ball aa29 no ball ab29 no ball ac29 no ball ad29 no ball aa30 no ball ab30 no ball ac30 no ball ad30 no ball aa31 ab31 ac31 ad31 aa32 ab32 ac32 ad32 aa33 ab33 ac33 ad33 aa34 ab34 ac34 ad34 signals listed by ball assignment (part 6 of 9) ball signal name ball signal name ball signal name ball signal name advance information powernp tm npe405h embedded processor data sheet 33 ae01 af01 ag01 ah01 ae02 af02 ag02 ah02 ae03 af03 ag03 ah03 ae04 af04 ag04 ah04 ae05 no ball af05 no ball ag05 no ball ah05 no ball ae06 no ball af06 no ball ag06 no ball ah06 no ball ae07 no ball af07 no ball ag07 no ball ah07 no ball ae08 no ball af08 no ball ag08 no ball ah08 no ball ae09 no ball af09 no ball ag09 no ball ah09 no ball ae10 no ball af10 no ball ag10 no ball ah10 no ball ae11 no ball af11 no ball ag11 no ball ah11 no ball ae12 no ball af12 no ball ag12 no ball ah12 no ball ae13 no ball af13 no ball ag13 no ball ah13 no ball ae14 no ball af14 no ball ag14 no ball ah14 no ball ae15 no ball af15 no ball ag15 no ball ah15 no ball ae16 no ball af16 no ball ag16 no ball ah16 no ball ae17 no ball af17 no ball ag17 no ball ah17 no ball ae18 no ball af18 no ball ag18 no ball ah18 no ball ae19 no ball af19 no ball ag19 no ball ah19 no ball ae20 no ball af20 no ball ag20 no ball ah20 no ball ae21 no ball af21 no ball ag21 no ball ah21 no ball ae22 no ball af22 no ball ag22 no ball ah22 no ball ae23 no ball af23 no ball ag23 no ball ah23 no ball ae24 no ball af24 no ball ag24 no ball ah24 no ball ae25 no ball af25 no ball ag25 no ball ah25 no ball ae26 no ball af26 no ball ag26 no ball ah26 no ball ae27 no ball af27 no ball ag27 no ball ah27 no ball ae28 no ball af28 no ball ag28 no ball ah28 no ball ae29 no ball af29 no ball ag29 no ball ah29 no ball ae30 no ball af30 no ball ag30 no ball ah30 no ball ae31 af31 ag31 ah31 ae32 af32 ag32 ah32 ae33 af33 ag33 ah33 ae34 af34 ag34 ah34 signals listed by ball assignment (part 7 of 9) ball signal name ball signal name ball signal name ball signal name advance information powernp tm npe405h embedded processor data sheet 34 aj01 ak01 al01 am01 aj02 ak02 al02 am02 aj03 ak03 al03 am03 aj04 ak04 al04 am04 aj05 no ball ak05 no ball al05 am05 aj06 no ball ak06 no ball al06 am06 aj07 no ball ak07 no ball al07 am07 aj08 no ball ak08 no ball al08 am08 aj09 no ball ak09 no ball al09 am09 aj10 no ball ak10 no ball al10 am10 aj11 no ball ak11 no ball al11 am11 aj12 no ball ak12 no ball al12 am12 aj13 no ball ak13 no ball al13 am13 aj14 no ball ak14 no ball al14 am14 aj15 no ball ak15 no ball al15 am15 aj16 no ball ak16 no ball al16 am16 aj17 no ball ak17 no ball al17 am17 aj18 no ball ak18 no ball al18 am18 aj19 no ball ak19 no ball al19 am19 aj20 no ball ak20 no ball al20 am20 aj21 no ball ak21 no ball al21 am21 aj22 no ball ak22 no ball al22 am22 aj23 no ball ak23 no ball al23 am23 aj24 no ball ak24 no ball al24 am24 aj25 no ball ak25 no ball al25 am25 aj26 no ball ak26 no ball al26 am26 aj27 no ball ak27 no ball al27 am27 aj28 no ball ak28 no ball al28 am28 aj29 no ball ak29 no ball al29 am29 aj30 no ball ak30 no ball al30 am30 aj31 ak31 al31 am31 aj32 ak32 al32 am32 aj33 ak33 al33 am33 aj34 ak34 al34 am34 signals listed by ball assignment (part 8 of 9) ball signal name ball signal name ball signal name ball signal name advance information powernp tm npe405h embedded processor data sheet 35 an01 ap01 an02 ap02 an03 ap03 an04 ap04 an05 ap05 an06 ap06 an07 ap07 an08 ap08 an09 ap09 an10 ap10 an11 ap11 an12 ap12 an13 ap13 an14 ap14 an15 ap15 an16 ap16 an17 ap17 an18 ap18 an19 ap19 an20 ap20 an21 ap21 an22 ap22 an23 ap23 an24 ap24 an25 ap25 an26 ap26 an27 ap27 an28 ap28 an29 ap29 an30 ap30 an31 ap31 an32 ap32 an33 ap33 an34 ap34 signals listed by ball assignment (part 9 of 9) ball signal name ball signal name ball signal name ball signal name advance information powernp tm npe405h embedded processor data sheet 36 signal list the table following table provides a summary of the number of package pins associated with each functional interface group. in the table ?ignal functional description?on page 37, each external signal is listed along with a short description of the signal function. the signals are grouped together according to their function. some signals are multiplexed on the same package pin (ball) so that the pin can be used for different functions. in most cases, the signal name is shown in this table without any multiplexed signal names that may be associated with it. in cases where multiplexed signals are in the same functional group, the names appear as a default signal followed by secondary signals in square brackets (for example, pcic0:3[be0:3 ]). active-low signals such as be0:3 are marked with an overline. any signal that is not the primary (default) signal on a multiplexed pin is shown in square backets. the active signal on a multiplexed pin is controlled by programming. it is expected that in any single application, a particular pin will always be programmed to serve the same function. the flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible. in addition to multiplexing, many pins are also multi-purpose. for example, emc0txerr[emc0tx1en] functions as an error output when the ethernet interface operates in mii mode, or as a transmit enable output when operating in rmii mode. another multi-purpose use occurs when the ebc peripheral controller address pins are used as outputs by the npe405h to broadcast an address to external slave devices when the npe405h has control of the external bus. however, when an external master gains ownership of the external bus, these same pins are used as inputs which are driven by the external master and received by the ebc in the npe405h. in this example, the pins are also bidirectional, serving as both inputs and outputs. the following table lists all of the i/o signals provided by the npe405h. please refer to ?ignals listed alphabetically?on page 15 for the pin number to which each signal is assigned. pin summary group no. of pins nonmultiplexed signals 259 multiplexed signals 79 total signal pins 338 av dd ov dd v dd gnd thermal (and gnd) 100 reserved 0 total pins 580 advance information powernp tm npe405h embedded processor data sheet 37 signal functional description (part 1 of 9) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k ? to 3.3v, 10k ? to 5v ) 3. must pull down (recommended value is 1k ? ) 4. if not used, must pull up (recommended value is 3k ? to 3.3v) 5. if not used, must pull down (recommended value is 1k ? ) signal name description i/o type notes pci interface pciad0:31 pci address/data bus. multiplexed address and data bus i/o 5v tolerant 3.3v pci 4 pcic0:3[be0:3 ] pci bus command or byte enable i/o 5v tolerant 3.3v pci 4 pciparity pci parity. parity is even across pciad0:31 and pcic0:3[be0:3 ]. pciparity is valid one cycle after either an address or data phase. the pci device that drove pciad0:31 is responsible for driving pciparity on the next pci bus clock. i/o 5v tolerant 3.3v pci 4 pciframe driven by the current pci bus master to indicate beginning and duration of a pci access. i/o 5v tolerant 3.3v pci 4 pciirdy driven by the current pci bus master. assertion of pciirdy indicates that the pci initiator is ready to transfer data. i/o 5v tolerant 3.3v pci 4 pcitrdy the target of the current pci transaction drives pcitrdy . assertion of pcitrdy indicates that the pci target is ready to transfer data. i/o 5v tolerant 3.3v pci 4 pcistop the target of the current pci transaction can assert pcistop to indicate to the requesting pci master that it wants to end the current transaction. i/o 5v tolerant 3.3v pci 4 pcidevsel driven by the target of the current pci transaction. a pci target asserts pcidevsel when it has decoded an address and command encoding and claims the transaction. i/o 5v tolerant 3.3v pci 4 pciidsel used during configuration cycles to select the pci slave interface for configuration i 5v tolerant 3.3v pci 5 pciserr used for reporting address parity errors or catastrophic failures detected by a pci target. i/o 5v tolerant 3.3v pci 4 pciperr used for reporting data parity errors on pci transactions. pciperr is driven active by the device receiving pciad0:31, pcic0:3[be0:3 ], and pciparity, two pci clocks following the data in which bad parity is detected. i/o 5v tolerant 3.3v pci 4 pciclk used as the asynchronous pci clock when in asynch mode. it is unused when the pci interface is operated synchronously with the plb bus. i 5v tolerant 3.3v pci 5 pcireset pci specific reset o 5v tolerant 3.3v pci pciint pci interrupt. open-drain output (two states; 0 or open circuit). o 5v tolerant 3.3v pci pcireq0 [gnt] req0 when internal arbiter is used, or gnt when external arbiter is used. i 5v tolerant 3.3v pci 4 pcireq1:5 used as pcireq1:5 input when internal arbiter is used i 5v tolerant 3.3v pci 4 pcignt0 [req] gnt0 when internal arbiter is used, or req when external arbiter is used o 5v tolerant 3.3v pci advance information powernp tm npe405h embedded processor data sheet 38 pcignt1:5 pcignt1:5 output when internal arbiter is used. o 5v tolerant 3.3v pci hdlcex interface hdlcextxclk transmit clock i 3.3v lvttl hdlcextxfs transmit frame synchronization i 3.3v lvttl hdlcextxdataa transmit data port a o 3.3v lvttl hdlcextxdatab transmit data port b o 3.3v lvttl hdlcexrxclk receive clock i 3.3v lvttl hdlcexrxfs receive frame synchronization i 3.3v lvttl hdlcexrxdataa receive data port a i 3.3v lvttl hdlcexrxdatab receive data port b i 3.3v lvttl [hdlcextxena] transmit enable port a o 5v tolerant 3.3v lvttl [hdlcextxenb] transmit enable port b o 5v tolerant 3.3v lvttl hdlcmp interface hdlcmptxclk0:3 transmit clock signal that controls the transmit bit rate o 3.3v lvttl [hdlcmptxclk4:7] transmit clock signal that controls the transmit bit rate o 5v tolerant 3.3v lvttl hdlcmptxdata0:3 transmit data signal o 3.3v lvttl [hdlcmptxdata4:7] transmit data signal o 5v tolerant 3.3v lvttl [hdlcmptxen0:7] transmit data enable signal that controls when the external buffer is tri-stated o 5v tolerant 3.3v lvttl hdlcmprxclk0:3 receive clock signal that controls the receive bit rate i 3.3v lvttl [hdlcmprxclk4:7] receive clock signal that controls the receive bit rate i 5v tolerant 3.3v lvttl hdlcmprxdata0:3 receive data signal i 3.3v lvttl [hdlcmprxdata4:7] receive data signal i 5v tolerant 3.3v lvttl ethernet interface emc0mdclk management data clock. the mdclk is sourced to the phy. management information is transferred synchronously with respect to this clock (mii, rmii, and smii). o 5v tolerant 3.3v lvttl emc0mdio management data input/output is a bidirectional signal between the ethernet controller and the phy. it is used to transfer control and status information (mii, rmii, and smii). i/o 5v tolerant 3.3v lvttl 1, 4 signal functional description (part 2 of 9) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k ? to 3.3v, 10k ? to 5v ) 3. must pull down (recommended value is 1k ? ) 4. if not used, must pull up (recommended value is 3k ? to 3.3v) 5. if not used, must pull down (recommended value is 1k ? ) signal name description i/o type notes advance information powernp tm npe405h embedded processor data sheet 39 emc0txd0[emc0tx0d0][emc0tx0d] emc0txd1[emc0tx0d1][emc0tx1d] emc0txd2[emc0tx1d0][emc0tx2d] emc0txd3[emc0tx1d1][emc0tx3d] transmit data. a nibble wide data bus towards the net. the data is synchronous with phy0txclk (mii 0[rmii 0 and 1][smii 0, 1, 2, and 3]). o 3.3v lvttl [emc1txd0][emc1tx2d0] [emc1txd1][emc1tx2d1] [emc1txd2][emc1tx3d0] [emc1txd3][emc1tx3d1] rmii transmit data (mii 1[rmii 0 and 1]). o 5v tolerant 3.3v lvttl emc0txen[emc0tx0en][emc0sync] transmit enable. this signal is driven by emac2 to the phy. data is valid during the active state of this signal. deassertion of this signal indicates end of frame transmission. this signal is synchronous with phytxclk (mii 0[rmii 0]). or smii sync. o 3.3v lvttl emc0txerr[emc0tx1en] transmit error. this signal is generated by the ethernet controller, is connected to the phy and is synchronous with the phy0txclk. it informs the phy that an error was detected (mii 0). or transmit enable [rmii 1]. o 5v tolerant 3.3v lvttl [emc1txen][emc1tx2en] transmit enable ([mii 1][rmii 2]). o 5v tolerant 3.3v lvttl [emc1txerr][emc1tx3en] transmit error. this signal is generated by the ethernet controller, is connected to the phy and is synchronous with the phy1txclk. it informs the phy that an error was detected ([mii 1]). or transmit enable [rmii 3]. o 5v tolerant 3.3v lvttl phy0col[phy0rx1er]l collision [receive error] signal from the phy. this is an asynchronous signal (mii 0). or receive error ([rmii 1]). i 5v tolerant 3.3v lvttl phy0crs[phy0crs0dv] carrier sense signal from the phy. this is an asynchronous signal (mii 0). or carrier sense data valid ([rmii 0]). i 5v tolerant 3.3v lvttl 1, 5 phy0rxclk receiver medium clock. this signal is generated by the phy (mii 0). i 5v tolerant 3.3v lvttl 1, 4 phy0rxd0[phy0rx0d0][phy0rx0d] phy0rxd1[phy0rx0d1][phy0rx1d] phy0rxd2[phy0rx1d0][phy0rx2d] phy0rxd3[phy0rx1d1][phy0rx3d] received data. this is a nibble wide bus from the phy. the data is synchronous with phy0rxclk (mii 0[rmii 0 and 1][smii 0, 1, 2, and 3]). i 5v tolerant 3.3v lvttl 1, 4 [phy1rxd0][phy1rx2d0] [phy1rxd1][phy1rx2d1] [phy1rxd2][phy1rx3d0] [phy1rxd3][phy1rx3d1] receive data (mii 1[rmii 0 and 1]). i 5v tolerant 3.3v lvttl signal functional description (part 3 of 9) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k ? to 3.3v, 10k ? to 5v ) 3. must pull down (recommended value is 1k ? ) 4. if not used, must pull up (recommended value is 3k ? to 3.3v) 5. if not used, must pull down (recommended value is 1k ? ) signal name description i/o type notes advance information powernp tm npe405h embedded processor data sheet 40 phy0rxdv[phy0crs1dv] receive data valid. data on the data bus is valid when this signal is activated. deassertion of this signal indicates end of the frame reception (mii 0). or carrier sense data valid ([rmii 1]) i 5v tolerant 3.3v lvttl 1, 5 phy0rxerr[phy0rx0er] receive error. this signal comes from the phy and is synchronous with phy0rxclk (mii 0 [rmii 0]). i 5v tolerant 3.3v lvttl 1, 5 phy0txclk[phy0refclk] transmit medium clock. this signal is generated the phy ([mii 0]). or reference clock [rmii and smii]. i 5v tolerant 3v lvttl 1, 4 [phy1col][phy1rx3er] collision [receive error] signal from the phy. this is an asynchronous signal ([mii 1]). or receive error. this signal comes from the phy and is synchronous with phy1rxclk ([rmii 3]). i 5v tolerant 3.3v lvttl 1, 5 [phy1crs][phy1crs2dv] carrier sense signal from the phy. this is an asynchronous signal ([mii 1]). or carrier sense data valid ([rmii 2]). i 5v tolerant 3.3v lvttl [phy1rxclk] receiver medium clock. this signal is generated by the phy ([mii 1]). i 5v tolerant 3.3v lvttl 1, 4 [phy1rxdv][phy1crs3dv] receive data valid ([mii 0]). or carrier sense data valid ([rmii 3]). i 5v tolerant 3.3v lvttl [phy1rxerr][phy1rx2er] receive error. this signal comes from the phy and is synchronous with phy1rxclk ([mii 1][rmii 2]). i 5v tolerant 3.3v lvttl [phy1txclk] transmit medium clock. this signal is generated the phy ([mii 1]). i 5v tolerant 3.3v lvttl 1, 4 sdram interface memdata0:31 memory data bus notes: 1. memdata0 is the most significant bit (msb). 2. memdata31 is the least significant bit (lsb). i/o 3.3v lvttl 4 memaddr12:0 memory address bus. notes: 1. memaddr12 is the most significant bit (msb). 2. memaddr0 is the least significant bit (lsb). o 3.3v lvttl signal functional description (part 4 of 9) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k ? to 3.3v, 10k ? to 5v ) 3. must pull down (recommended value is 1k ? ) 4. if not used, must pull up (recommended value is 3k ? to 3.3v) 5. if not used, must pull down (recommended value is 1k ? ) signal name description i/o type notes advance information powernp tm npe405h embedded processor data sheet 41 ba1:0 bank address supporting up to 4 internal banks o 3.3v lvttl ras row address strobe. o 3.3v lvttl cas column address strobe. o 3.3v lvttl dqm0:3 dqm for byte lanes 0 (memdata0:7), 1 (memdata8:15), 2 (memdata16:23), and 3 (memdata24:31) o 3.3v lvttl dqmcb dqm for ecc check bits. o 3.3v lvttl ecc0:7 ecc check bits 0:7. i/o 3.3v lvttl 4 banksel0:3 select up to four external sdram banks. o 3.3v lvttl we write enable. o 3.3v lvttl clken0:1 sdram clock enable. o 3.3v lvttl memclkout0:1 two copies of an sdram clock allows, in some cases, glueless sdram attachment without requiring this signal to be repowered by a pll or zero-delay buffer. o 3.3v lvttl external slave peripheral interface perdata0:31 peripheral data bus used by npe405h when not in external master mode, otherwise used by external master. note: perdata00 is the most significant bit (msb) on this bus. i/o 5v tolerant 3.3v lvttl 1 peraddr4:31 peripheral address bus used by npe405h when not in external master mode, otherwise used by external master. i/o 5v tolerant 3.3v lvttl 1 perpar0:3 peripheral byte parity signals. i/o 5v tolerant 3.3v lvttl 1 perwbe0: 3 as outputs, these pins can act as byte-enables which are valid for an entire cycle or as write-byte-enables which are valid for each byte on each data transfer, allowing partial word transactions. as outputs, pins are used by either peripheral controller or dma controller depending upon the type of transfer involved. used as inputs when external bus master owns the external interface. i/o 5v tolerant 3.3v lvttl 1, 2 perwe peripheral write enable. low when any of the four perwbe signals are low. i/o 5v tolerant 3.3v lvttl [percs0: 7 ] peripheral chip selects o 5v tolerant 3.3v lvttl 2 peroe used by either peripheral controller or dma controller depending upon the type of transfer involved. when the npe405h is the bus master, it enables the selected sdrams to drive the bus. o 5v tolerant 3.3v lvttl 2 signal functional description (part 5 of 9) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k ? to 3.3v, 10k ? to 5v ) 3. must pull down (recommended value is 1k ? ) 4. if not used, must pull up (recommended value is 3k ? to 3.3v) 5. if not used, must pull down (recommended value is 1k ? ) signal name description i/o type notes advance information powernp tm npe405h embedded processor data sheet 42 perr/w used by the npe405h when not in external master mode, as an output by either the peripheral controller or dma controller depending upon the type of transfer involved. high indicates a read from memory, low indicates a write to memory. otherwise it used by the external master as an input to indicate the direction of transfer. i/o 5v tolerant 3.3v lvttl 1 perready used by a peripheral slave to indicate it is ready to transfer data. i 5v tolerant 3.3v lvttl 1 perblast used by the npe405h when not in external master mode, otherwise used by external master. indicates the last transfer of a memory access. i/o 5v tolerant 3.3v lvttl 1, 4 perclk peripheral clock to be used by an external master and by synchronous peripheral slaves. o 5v tolerant 3.3v lvttl pererr used as an input to record external master and slave peripheral errors. i 5v tolerant 3.3v lvttl 1, 5 [dmareq0:3 ] used by slave peripherals to indicate they are prepared to transfer data. i 5v tolerant 3.3v lvttl 1, 5 [dmaack0:3 ] used by the npe405h to indicate that data transfers have occurred. o 5v tolerant 3.3v lvttl [eot0:3 ][tc0:3 ] end of transfer[terminal count]. i/o 5v tolerant 3.3v lvttl 1, 5 signal functional description (part 6 of 9) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k ? to 3.3v, 10k ? to 5v ) 3. must pull down (recommended value is 1k ? ) 4. if not used, must pull up (recommended value is 3k ? to 3.3v) 5. if not used, must pull down (recommended value is 1k ? ) signal name description i/o type notes advance information powernp tm npe405h embedded processor data sheet 43 external master peripheral interface extreset peripheral reset. used by an external master and synchronous peripheral slaves. o 5v tolerant 3.3v lvttl holdreq hold request. used by an external master to request ownership of the peripheral bus. i 5v tolerant 3.3v lvttl 1, 5 holdack hold acknowledge. used by the npe405h to transfer ownership of peripheral bus to an external master. o 5v tolerant 3.3v lvttl extreq external request. used by an external master to indicate it is prepared to transfer data. i 5v tolerant 3.3v lvttl 1, 4 extack exteranl acknowledgement. used by the npe405h to indicate that a data transfer occurred. o 5v tolerant 3.3v lvttl holdpri hold primary. used by an external master to indicate the priority of a given transfer (0 = high, 1 = low). i 5v tolerant 3.3v lvttl 1, 4 busreq bus request. used when the npe405h needs to regain control of peripheral interface from an external master. o 5v tolerant 3.3v lvttl internal peripheral interface uartserclk serial clock used to provide an alternative clock to the internally generated serial clock. used in cases where the allowable internally generated baud rates are not satisfactory. this input can be individually connected to either or both uart0 and uart1. i 5v tolerant 3.3v lvttl 1, 4 uart0_rx uart0 receive data. i 5v tolerant 3.3v lvttl 1, 4 uart0_tx uart0 transmit data. o 5v tolerant 3.3v lvttl [uart0_dcd ] uart0 data carrier detect. i 5v tolerant 3.3v lvttl 1, 4 [uart0_dsr ] uart0 data set ready. i 5v tolerant 3.3v lvttl 1, 4 [uart0_cts ] uart0 clear to send. i 5v tolerant 3.3v lvttl 1, 4 [uart0_dtr ] uart0 data terminal ready. o 5v tolerant 3.3v lvttl [uart0_rts ] uart0 request to send. o 5v tolerant 3.3v lvttl [uart0_ri ] uart0 ring indicator. i 5v tolerant 3.3v lvttl r 1, 4 signal functional description (part 7 of 9) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k ? to 3.3v, 10k ? to 5v ) 3. must pull down (recommended value is 1k ? ) 4. if not used, must pull up (recommended value is 3k ? to 3.3v) 5. if not used, must pull down (recommended value is 1k ? ) signal name description i/o type notes advance information powernp tm npe405h embedded processor data sheet 44 uart1_rx uart1 receive data. i 5v tolerant 3.3v lvttl 1, 4 uart1_tx uart1 transmit data. o 5v tolerant 3.3v lvttl [uart1_dcd ] uart1 data carrier detect. i 5v tolerant 3.3v lvttl 1, 4 [uart1_dsr ] uart1 data set ready. i 5v tolerant 3.3v lvttl 1, 4 [uart1_cts ] uart1 clear to send. i 5v tolerant 3.3v lvttl 1, 4 [uart1_dtr ] uart1 data terminal ready. o 5v tolerant 3.3v lvttl [uart1_rts ] uart1 request to send. o 5v tolerant 3.3v lvttl [uart1_ri ] uart1 ring indicator. i 5v tolerant 3.3v lvttl 1, 4 iicscl[iecscl] iic [initilization prom] serial clock. i/o 5v tolerant 3.3v lvttl 1, 2 iicsda[iecsda] iic [initilization prom] serial data. i/o 5v tolerant 3.3v lvttl 1, 2 interrupts interface [irq0:6] interrupt requests. i 5v tolerant 3.3v lvttl 1, 5 jtag interface tdi test data in. i 5v tolerant 3.3v lvttl 1, 4 tms test mode select. i 5v tolerant 3.3v lvttl 1, 4 tdo test data out. o 5v tolerant 3.3v lvttl tck test clock. i 5v tolerant 3.3v lvttl 1, 4 trst test reset. i 5v tolerant 3.3v lvttl 2, 5 signal functional description (part 8 of 9) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k ? to 3.3v, 10k ? to 5v ) 3. must pull down (recommended value is 1k ? ) 4. if not used, must pull up (recommended value is 3k ? to 3.3v) 5. if not used, must pull down (recommended value is 1k ? ) signal name description i/o type notes advance information powernp tm npe405h embedded processor data sheet 45 system interface sysclk main system clock input. i 3.3v analog wire w/esd sysreset main system reset. i/o 5v tolerant 3.3v lvttl 1, 2 syserr set to 1 when a machine check is generated. o 5v tolerant 3.3v lvttl halt halt from external debugger. i 5v tolerant 3.3v lvttl 1, 4 cgpio0:31 communicatons general purpose i/o. i/o 5v tolerant 3.3v lvttl sgpio0:31 system general purpose i/o. i/o 5v tolerant 3.3v lvttl testen test enable. used only for manufacturing tests. pull down for normal operation. i 3.3v lvttl rcvr w/ pd 3 tmrclk this input must toggle at a rate of less than one half the cpu core frequency (less than 100mhz in most cases). in most cases this input toggles much slower (in the 1mhz to 10mhz range). i 5v tolerant 3.3v lvttl 1, 4 trace interface [ts1e] [ts2e] even trace execution status.to access this function, software must toggle a dcr bit. o 5v tolerant 3.3v lvttl [ts1o] [ts2o] odd trace execution status. to access this function, software must toggle a dcr bit. o 5v tolerant 3.3v lvttl [ts3:6] trace status. to access this function, software must toggle a dcr bit. o 5v tolerant 3.3v lvttl [trcclk] trace interface clock. a toggling signal that is always half of the cpu core frequency. to access this function, software must toggle a dcr bit. o 5v tolerant 3.3v lvttl 1 power pins gnd ground note: j09-j14, k09-k14, l09-l14, m09-m14, n09-n14, and p09-p14 are also thermal balls. i hardwire v dd logic voltage?.5v i hardwire ov dd output driver voltage?.3v i hardwire av dd filtered pll voltage?.5v i 3.3v dc wire w/esd other pins reserved do not connect signals, voltage, or ground to these pins. n/a n/a signal functional description (part 9 of 9) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k ? to 3.3v, 10k ? to 5v ) 3. must pull down (recommended value is 1k ? ) 4. if not used, must pull up (recommended value is 3k ? to 3.3v) 5. if not used, must pull down (recommended value is 1k ? ) signal name description i/o type notes advance information powernp tm npe405h embedded processor data sheet 46 notes: 1. for a chip mounted on a jedec 2s2p card without a heat sink. 2. for a chip mounted on a card with at least one signal and two power planes, the following relationships exist: a. case temperature, t c , is measured at top center of case surface with device soldered to circuit board. b. t a = t c ?p ca , where t a is ambient temperature and p is power consumption. c. t cmax = t jmax ?p jc , where t jmax is maximum junction temperature and p is power consumption. absolute maximum ratings the absolute maximum ratings below are stress ratings only. operation at or beyond these maximum ratings can cause permanent damage to the device. characteristic symbol value unit supply voltage (internal logic) v dd 0 to 2.7 v supply voltage (i/o interface) ov dd 0 to 3.6 v pll supply voltage av dd 0 to 2.7 v input voltage (3.3v lvttl receivers) v in 0 to 3.6 v input voltage (5.0v lvttl receivers) v in 0 to 5.5 v storage temperature range t stg -55 to 150 c case temperature under bias t c -40 to +120 c package thermal speci?ations the npe405h is designed to operate within a case temperature range of -40?c to 120?c. thermal resistance values for the e-pbga packages in a convection environment are as follows: package?hermal resistance symbol air?w ft/min (m/sec) unit 0 (0) 100 (0.51) 200 (1.02) 35mm, 580-balls?unction-to-case jc ?/w 35mm, 580-balls?ase-to-ambient 1 ca ?/w advance information powernp tm npe405h embedded processor data sheet 47 recommended dc operating conditions device operation beyond the conditions speci?d is not recommended. extended operation beyond the recommended conditions can affect device reliability. notes: 1. pci drivers meet pci specifications. parameter symbol minimum typical maximum unit notes logic supply voltage v dd 2.3 2.5 2.7 v 1 i/o supply voltage ov dd 3.0 3.3 3.6 v 1 pll supply voltage av dd 2.3 2.5 2.7 v input logic high (3.3v lvttl receivers) v ih 2.0 ov dd v input logic high (5.0v lvttl receivers) v ih 2.0 5.5 v input logic low v il 0 0.8 v output logic high v oh 2.4 ov dd v output logic low v ol 0 0.4 v input leakage current (no pull-up or pull-down) i il1 00 a input leakage current for pull- down i il2 0 (lpdl) 400 (mpul) a input leakage current for pull-up i il3 ? 250 (lpdl) 0 (mpul) a input max allowable overshoot (3.3v lvttl receivers) v imao3 ov dd + 0.6 v input max allowable overshoot (5.0v lvttl receivers) v imao5 5.5 v input max allowable undershoot (3.3v or 5.0v receivers) v imau ? 0.6 v output max allowable overshoot (3.3v or 5.0v receivers) v omao ov dd + 0.3 v output max allowable undershoot (3.3v and 5.0v receivers) v omau3 ? 0.6 v case temperature t c ? 40 85 c advance information powernp tm npe405h embedded processor data sheet 48 test conditions clock timing and switching characteristics are specified in accordance with operating conditions shown in the table ?ecommended dc operating conditions.?ac specifications are characterized at v dd = 3.14v and t j = 100?c with the 50pf test load (c l ) shown in the figure at right. capacitance parameter symbol maximum unit notes input capacitance group 1 (3.3v lvttl //o) c in1 2.5 pf input capacitance group 2 (5v tolerant lvttl i/o) c in2 3.5 pf input capacitance group 3 (pci i/o) c in3 5.0 pf input capacitance group 1 (rx only pins) c in4 0.75 pf dc electrical characteristics parameter symbol minimum typical maximum unit active operating current (v dd )i dd 390 600 ma active operating current (ov dd )i odd 35 100 ma pll voltage (av dd )v pll 2.3 2.5 2.7 v pll v dd input current i pll 16 23 ma output pin c l c l = 50pf for all signals advance information powernp tm npe405h embedded processor data sheet 49 timing waveform sysclk and memclk timing symbol parameter min max units sysclk input f c sysclk clock input frequency 25 66.6 mhz t c sysclk clock period 15 40 ns t cs clock edge stability 0.15 ns t ch clock input high time 40% of nominal period 60% of nominal period ns t cl clock input low time 40% of nominal period 60% of nominal period ns note: input slew rate > 2v/ns memclk output f c memclk clock output frequency?00mhz 100 mhz t c memclk clock period?00mhz 10 ns f c memclk clock output frequency?66mhz 133 mhz t c memclk clock period?66mhz 7.5 ns t ch clock output high time 35% of nominal period 65% of nominal period ns t cl clock output low time 35% of nominal period 65% of nominal period ns t cl t ch t c 2.0v 1.5v 0.8v advance information powernp tm npe405h embedded processor data sheet 50 spread spectrum clocking care must be taken when using a spread spectrum clock generator (sscg) with the npe405h. this controller uses a pll for clock generation inside the chip. the accuracy with which the pll follows the sscg is referred to as tracking skew. the pll bandwidth and phase angle determine how much tracking skew there is between the sscg and the pll for a given frequency deviation and modulation frequency. when using an sscg with the npe405h the following conditions must be met: the frequency deviation must not violate the minimum clock cycle time. therefore, when operating the npe405h with one or more internal clocks at their maximum supported frequency, the sscg can only lower the frequency. the maximum frequency deviation cannot exceed ? 3%, and the modulation frequency cannot exceed 40khz. in some cases, on-board npe405h peripherals impose more stringent requirements (see note 1). use the peripheral bus clock for logic that is synchronous to the peripheral bus since this clock tracks the modulation. use the sdram memclk since it also tracks the modulation. notes: 1. the serial port baud rates are synchronous to the modulated clock. the serial port has a tolerance of approximately 1.5% on baud rate before framing errors begin to occur. the 1.5% tolerance assumes that the connected device is running at precise baud rates. if an external serial clock is used the baud rate is unaffected by the modulation 2. ethernet operation is unaffected. 3. iic operation is unaffected. 4. the pci clock specification for 66mhz allows a maximum frequency deviation of ? 1% at a modulation between 30khz and 33khz. pci asynchronous mode is unaffected. caution: it is up to the system designer to ensure that any sscg used with the npe405h meets the above requirements and does not adversely affect other aspects of the system. advance information powernp tm npe405h embedded processor data sheet 51 peripheral interface clock timings parameter min max units pciclk input frequency (asynchronous mode) note 2 66 mhz pciclk period (asynchronous mode) 15 note 2 ns pci clock frequency (synchronous mode) 25 33 mhz pci clock period (synchronous mode - note 3) 30 40 ns pciclk input high time 40% of nominal period 60% of nominal period ns pciclk input low time 40% of nominal period 60% of nominal period ns emc0mdclk output frequency 2.5 mhz emc0mdclk period 400 ns emc0mdclk output high time 160 ns emc0mdclk output low time 160 ns phy0txclk input frequency 2.5 25 mhz phy0txclk period 40 400 ns phy0txclk input high time 35% of nominal period ns phy0txclk input low time 35% of nominal period ns phy0rxclk input frequency 2.5 25 mhz phy0rxclk period 40 400 ns phy0rxclk input high time 35% of nominal period ns phy0rxclk input low time 35% of nominal period ns perclk output frequency?00mhz (for external master or synchronous slaves) 50 mhz perclk period?00mhz 20 ns perclk output frequency?66mhz (for external master or synchronous slaves) ?6 perclk period?66mhz 15 perclk output high time 50% of nominal period 66% of nominal period ns perclk output low time 33% of nominal period 50% of nominal period ns uartserclk input frequency (note 1) 1000/(2t opb +2ns) mhz uartserclk period 2t opb +2 ?s uartserclk input high time t opb +1 ?s uartserclk input low time t opb +1 ?s tmrclk input frequency?00mhz 50 mhz tmrclk period?00mhz 20 ns tmrclk input frequency?66mhz 66 tmrclk period?66mhz 15 tmrclk input high time 40% of nominal period 60% of nominal period ns tmrclk input low time 40% of nominal period 60% of nominal period ns notes: 1. t opb is the period in ns of the opb clock. the internal opb clock runs at 1/2 the frequency of the plb clock. the maximum opb clock frequency is 50 mhz for 200mhz parts and 66mhz.for 266mhz parts. 2. in asynchronous pci mode the minimum pciclk frequency is 1/8 the plb clock. refer to the npe405h user s manual for more information. 3. in synchronous pci mode the pci clock is derived from sysclk and the pciclk input pin is unused. advance information powernp tm npe405h embedded processor data sheet 52 input setup and hold waveform output delay and float timing waveform 1.5v sysclk 1.5v t is t ih min min inputs valid data bus (inputs) d0:31 min min t ih t is 1.5v valid valid valid t ov t oh 1.5v min outputs sysclk outputs t of min max max 1.5v 1.5v advance information powernp tm npe405h embedded processor data sheet 53 i/o speci?ations?00mhz (part 1 of 5) notes: 1. ethernet interface meets timing requirements as defined by ieee 802.3 standard. 2. the two-cycle sdram command interface is driven in cycle 1 and used in cycle 2. output times in table are in cycle 1. 3. sdram output timing is relative to the rising edge of the internal plb clock, which is an integral multiple of and rising- edge aligned with sysclk. therefore, sdram output timings in the table are shown relative to sysclk. timings shown are for a lumped 50pf load, however the interface has been verified for pc100-compliant operation using transmission line circuit analysis. 4. sdram memclkout0:1 rising edge at package pin precedes the internal plb clock by approximately 0.5ns for a typical clock network or a lumped 10pf load. 5. perclk rising edge at package pin with a 10pf load trails the internal plb clock by approximately 0.8ns. 6. pci timings are for asynchronous operation up to 66mhz. pci output hold time requirement is 1ns for 66mhz and 2ns for 33mhz. signal input (ns) output (ns) output current (ma) clock notes setup time (minimum) hold time (minimum) valid delay (maximum) 50pf load hold time (minimum) 50pf load i/o h (maximum) i/o l (minimum) pci interface pciad0:31 12.3 15.5 pciclk 6 pcic0:3[be3:0 ] 12.3 15.5 pciclk 6 pciclk n/a n/a n/a n/a async pcidevsel 12.3 15.5 pciclk 6 pciframe 12.3 15.5 pciclk 6 pcignt0 [req ] pcignt1:5 n/a n/a 12.3 15.5 pciclk 6 pciidsel n/a n/a pciclk 6 pciint [perwe ] n/a n/a 12.3 15.5 pciclk async pciirdy 12.3 15.5 pciclk 6 pciparity 12.3 15.5 pciclk 6 pciperr 12.3 15.5 pciclk 6 pcireq0 [gnt ] pcireq1:5 n/a n/a n/a n/a pciclk 6 pcireset n/a n/a n/a n/a 12.3 15.5 pciclk pciserr n/a n/a n/a n/a 12.3 15.5 pciclk pcistop 12.3 15.5 pciclk 6 pcitrdy 12.3 15.5 pciclk 6 ethernet interface emc0mdclk n/a n/a 7.4 1.5 12 8 1, async emc0mdio n/a n/a 8.8 1.2 12 8 emc0mdclk 1 emc0txd0:3 [emc0tx0:1d0:1 [emc0tx0:3d] n/a n/a 10.5 [7.3] [5.0] 3.0 [2.3] [1.7] 12 8 phytx 1 emc0txen [emc0tx0en] [emc0sync] n/a n/a 11.8 [7.2] [5.6] 2.9 [2.3] [1.7] 12 8 phytx 1 emc0txerr [emc0tx1en] n/a n/a 11.8[7.4] 2.9[2.4] 12 8 phytx 1 [emc1txd0:3] [emc1tx2:3d0:1] 12 8 [emc1txen] [emc1tx2en] 12 8 [emc1txerr] [emc1tx3en] 12 8 advance information powernp tm npe405h embedded processor data sheet 54 phy0col[phy0rx1er]l async[0.2] async[1.7] n/a n/a n/a n/a 1 phy0crs[phy0crs0dv] async[0.1] async[1.9] n/a n/a n/a n/a 1 phy0rxclk n/a n/a n/a n/a n/a n/a 1, async phy0rxd0:3 [phy0rx0:1d0:1] [phy0rx0:3d] 1.5 [0.8] [0.9] 1.7 [1.7] [0.3] n/a n/a n/a n/a phyrx 1 phy0rxdv [phy0crs1dv] 1.3[0.7] 1.7[1.7] n/a n/a n/a n/a phyrx 1 phy0rxerr[phy0rx0er] 1.3[0.7] 1.8[1.9] n/a n/a n/a n/a phyrx 1 phy0txclk[phy0refclk] n/a n/a n/a n/a n/a n/a 1, async [phy1rxd0:3] [phy1rx2:3d0:1] n/a n/a [phy1col] [phy1rx3er] n/a n/a [phy1crs] [phy1crs2dv] n/a n/a [phy1rxclk] n/a n/a [phy1rxdv] [phy1crs3dv] n/a n/a [phy1rxerr] [phy1rx2er] n/a n/a [phy1txclk] n/a n/a hdlcex interface hdlcexrxclk n/a n/a n/a n/a n/a n/a hdlcexrxdataa:b 23.8 2.1 n/a n/a n/a n/a hdlcexrxfs 24.2 1.1 n/a n/a n/a n/a hdlcextxclk n/a n/a n/a n/a n/a n/a hdlcextxdataa:b n/a n/a 10.5 3.3 12 8 hdlcextxfs 20.3 1.0 n/a n/a n/a n/a hdlcextxena [cgpio24][uart1_rts ] n/a n/a 11.3 3.5 12 8 hdlcextxenb [cgpio25][uart1_dtr ] n/a n/a 11.8 3.8 12 8 hdlcmp interface hdlcmptxclk0:3 n/a n/a [hdlcmptxclk4:7] n/a n/a hdlcmptxdata0:3 12 8 i/o speci?ations?00mhz (part 2 of 5) notes: 1. ethernet interface meets timing requirements as defined by ieee 802.3 standard. 2. the two-cycle sdram command interface is driven in cycle 1 and used in cycle 2. output times in table are in cycle 1. 3. sdram output timing is relative to the rising edge of the internal plb clock, which is an integral multiple of and rising- edge aligned with sysclk. therefore, sdram output timings in the table are shown relative to sysclk. timings shown are for a lumped 50pf load, however the interface has been verified for pc100-compliant operation using transmission line circuit analysis. 4. sdram memclkout0:1 rising edge at package pin precedes the internal plb clock by approximately 0.5ns for a typical clock network or a lumped 10pf load. 5. perclk rising edge at package pin with a 10pf load trails the internal plb clock by approximately 0.8ns. 6. pci timings are for asynchronous operation up to 66mhz. pci output hold time requirement is 1ns for 66mhz and 2ns for 33mhz. signal input (ns) output (ns) output current (ma) clock notes setup time (minimum) hold time (minimum) valid delay (maximum) 50pf load hold time (minimum) 50pf load i/o h (maximum) i/o l (minimum) advance information powernp tm npe405h embedded processor data sheet 55 [hdlcmptxdata4:7] 12 8 [hdlcmptxen0:7] 12 8 hdlcmprxclk0:3 n/a n/a [hdlcmprxclk4:7] n/a n/a hdlcmprxdata0:3 n/a n/a [hdlcmprxdata4:7] n/a n/a internal peripheral interface iicscl async async async async 17 11 iicsda async async async async 17 11 [uart0_cts ]cgpio26 async async n/a n/a n/a n/a [uart0_dcd ]cgpio28 async async n/a n/a n/a n/a [uart0_dsr ]cgpio27 async async n/a n/a n/a n/a [uart0_dtr ]cgpio31 n/a n/a async async 12 8 [uart0_ri ][cgpio29] async async n/a n/a n/a n/a [uart0_rts ]cgpio30 n/a n/a async async 12 8 uart0_rx async async n/a n/a n/a n/a uart0_tx n/a n/a async async 12 8 [uart1_cts ]cgpio20 async async n/a n/a n/a n/a [uart1_dcd ]cgpio22 async async n/a n/a n/a n/a [uart1_dsr ]cgpio21 async async n/a n/a n/a n/a [uart1_dtr ]cgpio25 n/a n/a async async 12 8 [uart1_ri ]cgpio23 async async n/a n/a n/a n/a [uart1_rts ]cgpio24 n/a n/a async async 12 8 uart1_rx async async n/a n/a n/a n/a uart1_tx n/a n/a async async 12 8 uartserclk async async n/a n/a n/a n/a interrupts interface [irq0:6]sgpio17:23 async async n/a n/a n/a n/a jtag interface tck async async n/a n/a n/a n/a tdi async async n/a n/a n/a n/a tdo n/a n/a async async 12 8 tms async async n/a n/a n/a n/a trst async async n/a n/a n/a n/a i/o speci?ations?00mhz (part 3 of 5) notes: 1. ethernet interface meets timing requirements as defined by ieee 802.3 standard. 2. the two-cycle sdram command interface is driven in cycle 1 and used in cycle 2. output times in table are in cycle 1. 3. sdram output timing is relative to the rising edge of the internal plb clock, which is an integral multiple of and rising- edge aligned with sysclk. therefore, sdram output timings in the table are shown relative to sysclk. timings shown are for a lumped 50pf load, however the interface has been verified for pc100-compliant operation using transmission line circuit analysis. 4. sdram memclkout0:1 rising edge at package pin precedes the internal plb clock by approximately 0.5ns for a typical clock network or a lumped 10pf load. 5. perclk rising edge at package pin with a 10pf load trails the internal plb clock by approximately 0.8ns. 6. pci timings are for asynchronous operation up to 66mhz. pci output hold time requirement is 1ns for 66mhz and 2ns for 33mhz. signal input (ns) output (ns) output current (ma) clock notes setup time (minimum) hold time (minimum) valid delay (maximum) 50pf load hold time (minimum) 50pf load i/o h (maximum) i/o l (minimum) advance information powernp tm npe405h embedded processor data sheet 56 system interface sgpio0 12 8 [trcclk]sgpio31 n/a n/a 11.2 1.2 12 8 [ts1e]sgpio1 n/a n/a 7.0 1.2 12 8 [ts2e]sgpio2 n/a n/a 7.0 1.2 12 8 [ts1o]sgpio3 n/a n/a 6.5 1.0 12 8 [ts2o]sgpio4 n/a n/a 6.4 1.0 12 8 [ts3]sgpio5 n/a n/a 6.4 1.0 12 8 [ts4]sgpio6 n/a n/a 6.4 1.0 12 8 [ts5]sgpio7 n/a n/a 6.6 1.0 12 8 [ts6]sgpio8 n/a n/a 6.4 1.0 12 8 halt async async n/a n/a n/a n/a sysclk n/a n/a n/a n/a n/a n/a syserr n/a n/a 5.3 1.7 12 8 sysreset n/a n/a n/a n/a 12 8 testen dc dc n/a n/a n/a n/a tmrclk n/a n/a async async n/a n/a sdram interface ba1:0 n/a n/a 7.2 1.5 19 12 sysclk 2, 3 banksel3:0 n/a n/a 5.8 1.0 19 12 sysclk 3 cas n/a n/a 7.0 1.4 19 12 sysclk 2, 3 clken0:1 n/a n/a 4.9 1.0 40 25 sysclk 3 dqm3:0 n/a n/a 5.9 1.0 19 12 sysclk 3 dqmcb n/a n/a 5.9 1.0 19 12 sysclk 3 ecc7:0 2.0 0.3 5.7 1.0 19 12 sysclk 3 memaddr12:0 n/a n/a 7.2 1.4 19 12 sysclk 2, 3 memclkout0:1 n/a n/a 0.4 -1.2 19 12 sysclk 3, 4 memdata31:0 2.0 0.3 5.6 1.0 19 12 sysclk 3 ras n/a n/a 7.4 1.6 19 12 sysclk 2, 3 we n/a n/a 7.1 1.4 19 12 sysclk 2, 3 i/o speci?ations?00mhz (part 4 of 5) notes: 1. ethernet interface meets timing requirements as defined by ieee 802.3 standard. 2. the two-cycle sdram command interface is driven in cycle 1 and used in cycle 2. output times in table are in cycle 1. 3. sdram output timing is relative to the rising edge of the internal plb clock, which is an integral multiple of and rising- edge aligned with sysclk. therefore, sdram output timings in the table are shown relative to sysclk. timings shown are for a lumped 50pf load, however the interface has been verified for pc100-compliant operation using transmission line circuit analysis. 4. sdram memclkout0:1 rising edge at package pin precedes the internal plb clock by approximately 0.5ns for a typical clock network or a lumped 10pf load. 5. perclk rising edge at package pin with a 10pf load trails the internal plb clock by approximately 0.8ns. 6. pci timings are for asynchronous operation up to 66mhz. pci output hold time requirement is 1ns for 66mhz and 2ns for 33mhz. signal input (ns) output (ns) output current (ma) clock notes setup time (minimum) hold time (minimum) valid delay (maximum) 50pf load hold time (minimum) 50pf load i/o h (maximum) i/o l (minimum) advance information powernp tm npe405h embedded processor data sheet 57 external slave peripheral interface dmareq0:3 [sgpio9:12] 4.8 0.0 7.0 1.1 n/a n/a perclk dmaack0:3 [sgpio13:16] n/a n/a 7.5 1.1 12 8 perclk eot0:3 [tc0:3 ] [sgpio24:27] 4.3 -0.1 8.5 1.2 12 8 perclk peraddr4:31 n/a n/a 8.5 0.9 17 11 perclk perblast n/a n/a 7.4 1.4 12 8 perclk percs0: 7 n/a n/a 7.2 1.3 12 8 perclk perdata0:31 4.8 1.0 9.3 1.0 17 11 perclk peroe n/a n/a 7.6 1.4 12 8 perclk perpar0:3 3.1 0.0 8.3 0.9 17 11 perclk perr/w n/a n/a 7.5 1.4 12 8 perclk perready 7.5 -0.5 n/a n/a n/a n/a perclk perwbe0: 3 n/a n/a 7.5 1.3 12 8 perclk perclk n/a n/a 0.5 -0.9 17 11 plb clk 5 pererr 4.0 -0.6 n/a n/a n/a n/a perclk external master peripheral interface busreq n/a n/a 8 0 12 8 perclk extack n/a n/a 7 0 12 8 perclk extreq 5 1 n/a n/a n/a n/a perclk extreset n/a n/a 8 0 19 12 perclk holdack n/a n/a 8 0 12 8 perclk holdpri 4 1 n/a n/a n/a n/a perclk holdreq 5 1 n/a n/a n/a n/a perclk i/o speci?ations?00mhz (part 5 of 5) notes: 1. ethernet interface meets timing requirements as defined by ieee 802.3 standard. 2. the two-cycle sdram command interface is driven in cycle 1 and used in cycle 2. output times in table are in cycle 1. 3. sdram output timing is relative to the rising edge of the internal plb clock, which is an integral multiple of and rising- edge aligned with sysclk. therefore, sdram output timings in the table are shown relative to sysclk. timings shown are for a lumped 50pf load, however the interface has been verified for pc100-compliant operation using transmission line circuit analysis. 4. sdram memclkout0:1 rising edge at package pin precedes the internal plb clock by approximately 0.5ns for a typical clock network or a lumped 10pf load. 5. perclk rising edge at package pin with a 10pf load trails the internal plb clock by approximately 0.8ns. 6. pci timings are for asynchronous operation up to 66mhz. pci output hold time requirement is 1ns for 66mhz and 2ns for 33mhz. signal input (ns) output (ns) output current (ma) clock notes setup time (minimum) hold time (minimum) valid delay (maximum) 50pf load hold time (minimum) 50pf load i/o h (maximum) i/o l (minimum) advance information powernp tm npe405h embedded processor data sheet 58 i/o speci?ations?66mhz (part 1 of 5) notes: 1. ethernet interface meets timing requirements as defined by ieee 802.3 standard. 2. the two-cycle sdram command interface is driven in cycle 1 and used in cycle 2. output times in table are in cycle 1. 3. sdram output timing is relative to the rising edge of the internal plb clock, which is an integral multiple of and rising- edge aligned with sysclk. therefore, sdram output timings in the table are shown relative to sysclk. timings shown are for a lumped 50pf load, however the interface has been verified for pc100-compliant operation using transmission line circuit analysis. 4. sdram memclkout0:1 rising edge at package pin precedes the internal plb clock by approximately 0.5ns for a typical clock network or a lumped 10pf load. 5. perclk rising edge at package pin with a 10pf load trails the internal plb clock by approximately 0.8ns. 6. pci timings are for asynchronous operation up to 66mhz. pci output hold time requirement is 1ns for 66mhz and 2ns for 33mhz. signal input (ns) output (ns) output current (ma) clock notes setup time (minimum) hold time (minimum) valid delay (maximum) 50pf load hold time (minimum) 50pf load i/o h (maximum) i/o l (minimum) pci interface pciad0:31 12.3 15.5 pciclk 6 pcic0:3[be3:0 ] 12.3 15.5 pciclk 6 pciclk n/a n/a n/a n/a async pcidevsel 12.3 15.5 pciclk 6 pciframe 12.3 15.5 pciclk 6 pcignt0 [req ] pcignt1:5 n/a n/a 12.3 15.5 pciclk 6 pciidsel n/a n/a pciclk 6 pciint [perwe ] n/a n/a 12.3 15.5 pciclk async pciirdy 12.3 15.5 pciclk 6 pciparity 12.3 15.5 pciclk 6 pciperr 12.3 15.5 pciclk 6 pcireq0 [gnt ] pcireq1:5 n/a n/a n/a n/a pciclk 6 pcireset n/a n/a n/a n/a 12.3 15.5 pciclk pciserr n/a n/a n/a n/a 12.3 15.5 pciclk pcistop 12.3 15.5 pciclk 6 pcitrdy 12.3 15.5 pciclk 6 ethernet interface emc0mdclk n/a n/a 7.4 1.5 12 8 1, async emc0mdio n/a n/a 6.7 1.2 12 8 emc0mdclk 1 emc0txd0:3 [emc0tx0:1d0:1 [emc0tx0:3d] n/a n/a 7.7 [5.6] [4.6] 3.0 [2.3] [1.7] 12 8 phytx 1 emc0txen [emc0tx0en] [emc0sync] n/a n/a 9.4 [5.5] [4.2] 2.9 [2.3] [1.7] 12 8 phytx 1 emc0txerr [emc0tx1en] n/a n/a 9.4[5.7] 2.9[2.4] 12 8 phytx 1 [emc1txd0:3] [emc1tx2:3d0:1] 12 8 [emc1txen] [emc1tx2en] 12 8 [emc1txerr] [emc1tx3en] 12 8 advance information powernp tm npe405h embedded processor data sheet 59 phy0col[phy0rx1er]l async[0.1] async[1.4] n/a n/a n/a n/a 1 phy0crs[phy0crs0dv] async[0.1] async[1.5] n/a n/a n/a n/a 1 phy0rxclk n/a n/a n/a n/a n/a n/a 1, async phy0rxd0:3 [phy0rx0:1d0:1] [phy0rx0:3d] 1.5 [0.8] [0.8] 1.4 [1.3] [0.2] n/a n/a n/a n/a phyrx 1 phy0rxdv [phy0crs1dv] 1.3[0.7] 1.3[1.3] n/a n/a n/a n/a phyrx 1 phy0rxerr[phy0rx0er] 1.3[0.7] 1.4[1.5] n/a n/a n/a n/a phyrx 1 phy0txclk[phy0refclk] n/a n/a n/a n/a n/a n/a 1, async [phy1rxd0:3] [phy1rx2:3d0:1] n/a n/a [phy1col] [phy1rx3er] n/a n/a [phy1crs] [phy1crs2dv] n/a n/a [phy1rxclk] n/a n/a [phy1rxdv] [phy1crs3dv] n/a n/a [phy1rxerr] [phy1rx2er] n/a n/a [phy1txclk] n/a n/a hdlcex interface hdlcexrxclk n/a n/a n/a n/a n/a n/a hdlcexrxdataa:b 23.8 1.5 n/a n/a n/a n/a hdlcexrxfs 24.2 0.8 n/a n/a n/a n/a hdlcextxclk n/a n/a n/a n/a n/a n/a hdlcextxdataa:b n/a n/a 7.6 3.3 12 8 hdlcextxfs 24.2 0.8 n/a n/a n/a n/a hdlcextxena [cgpio24][uart1_rts ] n/a n/a 8.5 3.5 12 8 hdlcextxenb [cgpio25][uart1_dtr ] n/a n/a 8.9/ 3.8 12 8 hdlcmp interface hdlcmptxclk0:3 n/a n/a [hdlcmptxclk4:7] n/a n/a hdlcmptxdata0:3 12 8 i/o speci?ations?66mhz (part 2 of 5) notes: 1. ethernet interface meets timing requirements as defined by ieee 802.3 standard. 2. the two-cycle sdram command interface is driven in cycle 1 and used in cycle 2. output times in table are in cycle 1. 3. sdram output timing is relative to the rising edge of the internal plb clock, which is an integral multiple of and rising- edge aligned with sysclk. therefore, sdram output timings in the table are shown relative to sysclk. timings shown are for a lumped 50pf load, however the interface has been verified for pc100-compliant operation using transmission line circuit analysis. 4. sdram memclkout0:1 rising edge at package pin precedes the internal plb clock by approximately 0.5ns for a typical clock network or a lumped 10pf load. 5. perclk rising edge at package pin with a 10pf load trails the internal plb clock by approximately 0.8ns. 6. pci timings are for asynchronous operation up to 66mhz. pci output hold time requirement is 1ns for 66mhz and 2ns for 33mhz. signal input (ns) output (ns) output current (ma) clock notes setup time (minimum) hold time (minimum) valid delay (maximum) 50pf load hold time (minimum) 50pf load i/o h (maximum) i/o l (minimum) advance information powernp tm npe405h embedded processor data sheet 60 [hdlcmptxdata4:7] 12 8 [hdlcmptxen0:7] 12 8 hdlcmprxclk0:3 n/a n/a [hdlcmprxclk4:7] n/a n/a hdlcmprxdata0:3 n/a n/a [hdlcmprxdata4:7] n/a n/a internal peripheral interface iicscl async async async async 17 11 iicsda async async async async 17 11 [uart0_cts ]cgpio26 async async n/a n/a n/a n/a [uart0_dcd ]cgpio28 async async n/a n/a n/a n/a [uart0_dsr ]cgpio27 async async n/a n/a n/a n/a [uart0_dtr ]cgpio31 n/a n/a async async 12 8 [uart0_ri ][cgpio29] async async n/a n/a n/a n/a [uart0_rts ]cgpio30 n/a n/a async async 12 8 uart0_rx async async n/a n/a n/a n/a uart0_tx n/a n/a async async 12 8 [uart1_cts ]cgpio20 async async n/a n/a n/a n/a [uart1_dcd ]cgpio22 async async n/a n/a n/a n/a [uart1_dsr ]cgpio21 async async n/a n/a n/a n/a [uart1_dtr ]cgpio25 n/a n/a async async 12 8 [uart1_ri ]cgpio23 async async n/a n/a n/a n/a [uart1_rts ]cgpio24 n/a n/a async async 12 8 uart1_rx async async n/a n/a n/a n/a uart1_tx n/a n/a async async 12 8 uartserclk async async n/a n/a n/a n/a interrupts interface [irq0:6]sgpio17:23 async async n/a n/a n/a n/a jtag interface tck async async n/a n/a n/a n/a tdi async async n/a n/a n/a n/a tdo n/a n/a async async 12 8 tms async async n/a n/a n/a n/a trst async async n/a n/a n/a n/a i/o speci?ations?66mhz (part 3 of 5) notes: 1. ethernet interface meets timing requirements as defined by ieee 802.3 standard. 2. the two-cycle sdram command interface is driven in cycle 1 and used in cycle 2. output times in table are in cycle 1. 3. sdram output timing is relative to the rising edge of the internal plb clock, which is an integral multiple of and rising- edge aligned with sysclk. therefore, sdram output timings in the table are shown relative to sysclk. timings shown are for a lumped 50pf load, however the interface has been verified for pc100-compliant operation using transmission line circuit analysis. 4. sdram memclkout0:1 rising edge at package pin precedes the internal plb clock by approximately 0.5ns for a typical clock network or a lumped 10pf load. 5. perclk rising edge at package pin with a 10pf load trails the internal plb clock by approximately 0.8ns. 6. pci timings are for asynchronous operation up to 66mhz. pci output hold time requirement is 1ns for 66mhz and 2ns for 33mhz. signal input (ns) output (ns) output current (ma) clock notes setup time (minimum) hold time (minimum) valid delay (maximum) 50pf load hold time (minimum) 50pf load i/o h (maximum) i/o l (minimum) advance information powernp tm npe405h embedded processor data sheet 61 system interface sgpio0 12 8 [trcclk]sgpio31 n/a n/a 8.7 1.2 12 8 [ts1e]sgpio1 n/a n/a 5.8 1.2 12 8 [ts2e]sgpio2 n/a n/a 5.7 1.2 12 8 [ts1o]sgpio3 n/a n/a 5.3 1.0 12 8 [ts2o]sgpio4 n/a n/a 5.3 1.0 12 8 [ts3]sgpio5 n/a n/a 5.3 1.0 12 8 [ts4]sgpio6 n/a n/a 5.3 1.0 12 8 [ts5]sgpio7 n/a n/a 5.4 1.0 12 8 [ts6]sgpio8 n/a n/a 5.3 1.0 12 8 halt async async n/a n/a n/a n/a sysclk n/a n/a n/a n/a n/a n/a syserr n/a n/a 5.3 1.7 12 8 sysreset n/a n/a n/a n/a 12 8 testen dc dc n/a n/a n/a n/a tmrclk n/a n/a async async n/a n/a sdram interface ba1:0 n/a n/a 5.5 1.5 19 12 sysclk 1, 2 bankse 3:0 n/a n/a 4.6 1.0 19 12 sysclk 2 cas n/a n/a 5.3 1.4 19 12 sysclk 1, 2 clken0:1 n/a n/a 3.9 1.0 40 25 sysclk 2 dqm3:0 n/a n/a 4.7 1.0 19 12 sysclk 2 dqmcb n/a n/a 4.7 1.0 19 12 sysclk 2 ecc7:0 1.8 0.3 4.5 1.0 19 12 sysclk 2 memaddr12:0 n/a n/a 5.5 1.4 19 12 sysclk 1, 2 memclkout0:1 n/a n/a 0.4 -1.2 19 12 sysclk 2, 3 memdata31:0 1.8 0.3 4.4 1.0 19 12 sysclk 2 ras n/a n/a 5.7 1.6 19 12 sysclk 1, 2 we n/a n/a 5.4 1.4 19 12 sysclk 1, 2 i/o speci?ations?66mhz (part 4 of 5) notes: 1. ethernet interface meets timing requirements as defined by ieee 802.3 standard. 2. the two-cycle sdram command interface is driven in cycle 1 and used in cycle 2. output times in table are in cycle 1. 3. sdram output timing is relative to the rising edge of the internal plb clock, which is an integral multiple of and rising- edge aligned with sysclk. therefore, sdram output timings in the table are shown relative to sysclk. timings shown are for a lumped 50pf load, however the interface has been verified for pc100-compliant operation using transmission line circuit analysis. 4. sdram memclkout0:1 rising edge at package pin precedes the internal plb clock by approximately 0.5ns for a typical clock network or a lumped 10pf load. 5. perclk rising edge at package pin with a 10pf load trails the internal plb clock by approximately 0.8ns. 6. pci timings are for asynchronous operation up to 66mhz. pci output hold time requirement is 1ns for 66mhz and 2ns for 33mhz. signal input (ns) output (ns) output current (ma) clock notes setup time (minimum) hold time (minimum) valid delay (maximum) 50pf load hold time (minimum) 50pf load i/o h (maximum) i/o l (minimum) advance information powernp tm npe405h embedded processor data sheet 62 external slave peripheral interface dmareq0:3 [sgpio9:12] 4.1 0.0 5.5 1.1 n/a n/a perclk dmaack0:3 [sgpio13:16] n/a n/a 5.8 1.1 12 8 perclk eot0:3 [tc0:3 ] [sgpio24:27] 3.7 -0.1 6.7 1.2 12 8 perclk peraddr4:31 n/a n/a 6.5 0.9 17 11 perclk perblast n/a n/a 5.6 1.4 12 8 perclk percs0:3 n/a n/a 5.5 1.3 12 8 perclk perdata0:31 3.9 1.0 7.1 1.0 17 11 perclk peroe n/a n/a 5.7 1.4 12 8 perclk perpar0:3 2.7 0.0 6.4 0.9 17 11 perclk perr/w n/a n/a 5.7 1.4 12 8 perclk perready 6.2 -0.5 n/a n/a n/a n/a perclk perwbe0: 3 n/a n/a 5.7 1.3 12 8 perclk perclk n/a n/a 0.5 -0.9 17 11 plb clk 4 pererr 3.5 -0.6 n/a n/a n/a n/a perclk external master peripheral interface busreq n/a n/a 12 8 perclk extack n/a n/a 12 8 perclk extreq n/a n/a n/a n/a perclk extreset n/a n/a 19 12 perclk holdack n/a n/a 12 8 perclk holdpri n/a n/a n/a n/a perclk holdreq n/a n/a n/a n/a perclk i/o speci?ations?66mhz (part 5 of 5) notes: 1. ethernet interface meets timing requirements as defined by ieee 802.3 standard. 2. the two-cycle sdram command interface is driven in cycle 1 and used in cycle 2. output times in table are in cycle 1. 3. sdram output timing is relative to the rising edge of the internal plb clock, which is an integral multiple of and rising- edge aligned with sysclk. therefore, sdram output timings in the table are shown relative to sysclk. timings shown are for a lumped 50pf load, however the interface has been verified for pc100-compliant operation using transmission line circuit analysis. 4. sdram memclkout0:1 rising edge at package pin precedes the internal plb clock by approximately 0.5ns for a typical clock network or a lumped 10pf load. 5. perclk rising edge at package pin with a 10pf load trails the internal plb clock by approximately 0.8ns. 6. pci timings are for asynchronous operation up to 66mhz. pci output hold time requirement is 1ns for 66mhz and 2ns for 33mhz. signal input (ns) output (ns) output current (ma) clock notes setup time (minimum) hold time (minimum) valid delay (maximum) 50pf load hold time (minimum) 50pf load i/o h (maximum) i/o l (minimum) advance information powernp tm npe405h embedded processor data sheet 63 initialization the following describes the method by which initial chip settings are established when a system reset occurs. eeprom the default initial conditions can be read from a serial eeprom. advance information powernp tm npe405h embedded processor data sheet 64 (c) copyright international business machines corporation 1999, 2000 all rights reserved printed in the united states of america november 2000 the following are trademarks of international business machines corporation in the united states, or other countries, or both: other company, product, and service names may be trademarks or service marks of others. preliminary edition (11/22/00) this document contains information on a new product under development by ibm. ibm reserves the right to change or discontinue this product without notice. this document is a preliminary edition of the powernp npe405h data sheet . make sure you are using the correct edition for the level of the product. while the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. all information contained in this document is subject to change without notice. the products described in this document are not intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. the information contained in this document does not affect or change ibm product specifications or warranties. nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third parties. all information contained in this document was obtained in specific environments, and is presented as an illustration. the results obtained in other operating environments may vary. the information contained in this document is provided on an "as is" basis. in no event will ibm be liable for damages arising directly or indirectly from any use of the information contained in this document. ibm microelectronics division 1580 route 52 hopewell junction, ny 12533-6351 the ibm home page is www. ibm.com . the ibm microelectronics division home is www.chips.ibm.com . sa14-2557-00 blue logic coreconnect ibm logo codepack ibm powerpc |
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